TMS320F28388D: Input parameters of subroutine are wrong optimized.

Hidehiko Kaya

Intellectual 700 points

Part Number: TMS320F28388D

Hi Experts,

ti-cgt-c2000_21.6.0.LTS

It generates wrong code with optlv=2, speed=lv4

ADCSOC0CTL.bit.CHSEL (=input pin of SOC0) is wrong set.

Could let me know why CGT optimize incorrectly ?

/*PrivateFunction*/
static void ad_x_cfg_soc( UINT16 block, INT16 soc, UINT16 pin, UINT16 sh_time, UINT16 trg ){

  volatile struct ADC_REGS  * adcRegs_pst;
  UINT16 acqps_u16;

  adcRegs_pst = _mwadRegTbl_as[ block];
  acqps_u16 = (sh_time + MWAD_SYSCLK_TIME - 1)/MWAD_SYSCLK_TIME - 1U;

  EALLOW;

  switch( soc ){
  case 0: /* SOC 0 */
    adcRegs_pst->ADCSOC0CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC0CTL.bit.CHSEL = pin;
    adcRegs_pst->ADCSOC0CTL.bit.TRIGSEL = trg;
    break;
  case 1: /* SOC 1 */
    adcRegs_pst->ADCSOC1CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC1CTL.bit.CHSEL = pin;
    adcRegs_pst->ADCSOC1CTL.bit.TRIGSEL = trg;
    break;
  case 2: /* SOC 2 */
    adcRegs_pst->ADCSOC2CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC2CTL.bit.CHSEL = pin;
    adcRegs_pst->ADCSOC2CTL.bit.TRIGSEL = trg;
    break;
  case 3: /* SOC 3 */
    adcRegs_pst->ADCSOC3CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC3CTL.bit.CHSEL = pin;
    adcRegs_pst->ADCSOC3CTL.bit.TRIGSEL = trg;
    break;
  case 4: /* SOC 4 */
    adcRegs_pst->ADCSOC4CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC4CTL.bit.CHSEL = pin;
    adcRegs_pst->ADCSOC4CTL.bit.TRIGSEL = trg;
    break;
  case 5: /* SOC 5 */
    adcRegs_pst->ADCSOC5CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC5CTL.bit.CHSEL = pin;
    adcRegs_pst->ADCSOC5CTL.bit.TRIGSEL = trg;
    break;
  case 6: /* SOC 6 */
    adcRegs_pst->ADCSOC6CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC6CTL.bit.CHSEL = pin;
    adcRegs_pst->ADCSOC6CTL.bit.TRIGSEL = trg;
    break;
  case 7: /* SOC 7 */
    adcRegs_pst->ADCSOC7CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC7CTL.bit.CHSEL = pin;
    adcRegs_pst->ADCSOC7CTL.bit.TRIGSEL = trg;
    break;

  case 8: /* SOC 8 */
    adcRegs_pst->ADCSOC8CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC8CTL.bit.CHSEL = pin;
    adcRegs_pst->ADCSOC8CTL.bit.TRIGSEL = trg;
    break;
  case 9: /* SOC 9 */
    adcRegs_pst->ADCSOC9CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC9CTL.bit.CHSEL = pin;
    adcRegs_pst->ADCSOC9CTL.bit.TRIGSEL = trg;
    break;
  case 10:  /* SOC 10 */
    adcRegs_pst->ADCSOC10CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC10CTL.bit.CHSEL = pin;
    adcRegs_pst->ADCSOC10CTL.bit.TRIGSEL = trg;
    break;
  case 11:  /* SOC 11 */
    adcRegs_pst->ADCSOC11CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC11CTL.bit.CHSEL = pin;
    adcRegs_pst->ADCSOC11CTL.bit.TRIGSEL = trg;
    break;
  case 12:  /* SOC 12 */
    adcRegs_pst->ADCSOC12CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC12CTL.bit.CHSEL = pin;
    adcRegs_pst->ADCSOC12CTL.bit.TRIGSEL = trg;
    break;
  case 13:  /* SOC 13 */
    adcRegs_pst->ADCSOC13CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC13CTL.bit.CHSEL = pin;
    adcRegs_pst->ADCSOC13CTL.bit.TRIGSEL = trg;
    break;
  case 14:  /* SOC 14 */
    adcRegs_pst->ADCSOC14CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC14CTL.bit.CHSEL = pin;
    adcRegs_pst->ADCSOC14CTL.bit.TRIGSEL = trg;
    break;
  case 15:  /* SOC 15 */
    adcRegs_pst->ADCSOC15CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC15CTL.bit.CHSEL = pin;
    adcRegs_pst->ADCSOC15CTL.bit.TRIGSEL = trg;
    break;

  default:
    break;
  }

  EDIS;
}

I change this code to eliminate optimization for input parameters like below.

static void ad_x_cfg_soc( UINT16 block, INT16 soc, UINT16 pin, UINT16 sh_time, UINT16 trg ){

  volatile struct ADC_REGS  * adcRegs_pst;
  volatile UINT16 acqps_u16;
  volatile INT16 soc_s16 = soc;
  volatile UINT16 pin_u16 = pin;
  volatile UINT16 trg_u16 = trg;

  acqps_u16 = (sh_time + (UINT16)MWAD_SYSCLK_TIME - 1U)/(UINT16)MWAD_SYSCLK_TIME - 1U;

  adcRegs_pst = _mwadRegTbl_as[ block];

  EALLOW;

  switch( soc_s16 ){
  case 0: /* SOC 0 */
    adcRegs_pst->ADCSOC0CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC0CTL.bit.CHSEL = pin_u16;
    adcRegs_pst->ADCSOC0CTL.bit.TRIGSEL = trg_u16;
    break;
  case 1: /* SOC 1 */
    adcRegs_pst->ADCSOC1CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC1CTL.bit.CHSEL = pin_u16;
    adcRegs_pst->ADCSOC1CTL.bit.TRIGSEL = trg_u16;
    break;
  case 2: /* SOC 2 */
    adcRegs_pst->ADCSOC2CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC2CTL.bit.CHSEL = pin_u16;
    adcRegs_pst->ADCSOC2CTL.bit.TRIGSEL = trg_u16;
    break;
  case 3: /* SOC 3 */
    adcRegs_pst->ADCSOC3CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC3CTL.bit.CHSEL = pin_u16;
    adcRegs_pst->ADCSOC3CTL.bit.TRIGSEL = trg_u16;
    break;
  case 4: /* SOC 4 */
    adcRegs_pst->ADCSOC4CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC4CTL.bit.CHSEL = pin_u16;
    adcRegs_pst->ADCSOC4CTL.bit.TRIGSEL = trg_u16;
    break;
  case 5: /* SOC 5 */
    adcRegs_pst->ADCSOC5CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC5CTL.bit.CHSEL = pin_u16;
    adcRegs_pst->ADCSOC5CTL.bit.TRIGSEL = trg_u16;
    break;
  case 6: /* SOC 6 */
    adcRegs_pst->ADCSOC6CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC6CTL.bit.CHSEL = pin_u16;
    adcRegs_pst->ADCSOC6CTL.bit.TRIGSEL = trg_u16;
    break;
  case 7: /* SOC 7 */
    adcRegs_pst->ADCSOC7CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC7CTL.bit.CHSEL = pin_u16;
    adcRegs_pst->ADCSOC7CTL.bit.TRIGSEL = trg_u16;
    break;

  case 8: /* SOC 8 */
    adcRegs_pst->ADCSOC8CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC8CTL.bit.CHSEL = pin_u16;
    adcRegs_pst->ADCSOC8CTL.bit.TRIGSEL = trg_u16;
    break;
  case 9: /* SOC 9 */
    adcRegs_pst->ADCSOC9CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC9CTL.bit.CHSEL = pin_u16;
    adcRegs_pst->ADCSOC9CTL.bit.TRIGSEL = trg_u16;
    break;
  case 10:  /* SOC 10 */
    adcRegs_pst->ADCSOC10CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC10CTL.bit.CHSEL = pin_u16;
    adcRegs_pst->ADCSOC10CTL.bit.TRIGSEL = trg_u16;
    break;
  case 11:  /* SOC 11 */
    adcRegs_pst->ADCSOC11CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC11CTL.bit.CHSEL = pin_u16;
    adcRegs_pst->ADCSOC11CTL.bit.TRIGSEL = trg_u16;
    break;
  case 12:  /* SOC 12 */
    adcRegs_pst->ADCSOC12CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC12CTL.bit.CHSEL = pin_u16;
    adcRegs_pst->ADCSOC12CTL.bit.TRIGSEL = trg_u16;
    break;
  case 13:  /* SOC 13 */
    adcRegs_pst->ADCSOC13CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC13CTL.bit.CHSEL = pin_u16;
    adcRegs_pst->ADCSOC13CTL.bit.TRIGSEL = trg_u16;
    break;
  case 14:  /* SOC 14 */
    adcRegs_pst->ADCSOC14CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC14CTL.bit.CHSEL = pin_u16;
    adcRegs_pst->ADCSOC14CTL.bit.TRIGSEL = trg_u16;
    break;
  case 15:  /* SOC 15 */
    adcRegs_pst->ADCSOC15CTL.bit.ACQPS = acqps_u16;
    adcRegs_pst->ADCSOC15CTL.bit.CHSEL = pin_u16;
    adcRegs_pst->ADCSOC15CTL.bit.TRIGSEL = trg_u16;
    break;

  default:
    break;
  }

  EDIS;
}

And I checked if code work as expected, and which opt_level is related to this issue.

--opt_level	Result
off	OK
0	OK
1	NG

_mwad_OK_opt0.asm _mwad_ERR_opt1.asm

I attached assemble files.

Best regards,

Hidehiko

over 3 years ago

0 George Mock over 3 years ago

TI__Guru**** 252560 points

Please describe all the details regarding ...

Hidehiko Kaya said:
ADCSOC0CTL.bit.CHSEL (=input pin of SOC0) is wrong set.

Exactly what do you see that lets you know the problem occurred? What do you expect to see instead?

I need to build the code to be able to investigate the problem. I'm not sure whether to consider the code that is without, or with, the extra volatile local variables.

Put the code in the form you want me to investigate. Then for that source file, please follow the directions in the article How to Submit a Compiler Test Case.

Thanks and regards,

-George

0 Hidehiko Kaya over 3 years ago in reply to George Mock

Intellectual 700 points

Hi George,

Thank you for your reply.

>Please describe all the details regarding ...

>>Hidehiko Kaya said:
>>ADCSOC0CTL.bit.CHSEL (=input pin of SOC0) is wrong set.

Our code set SOC0 on ADC A, B, C, D with ad_x_cfg_soc().

Our design is below
ADC A channel select(CHSEL): SOC0=2, SOC1=4, SOC2=14
ADC B : SOC0=2, SOC1=4
ADC C : SOC0=2,
Wrong case (example= there are several patterns)
ADC A channel select(CHSEL): SOC0=4, SOC1=4, SOC2=14
ADC B : SOC0=4, SOC1=4
ADC C : SOC0=4,

There are some wrong case with same ad_x_cfg_soc().
We checked following points.
- input parameters are broken (unexpected wrong write).
(because they are global variable)
- stack overflow
- logging input values, local variable to set register fields in ad_x_cfg_soc().
-> input values are correct but local variables are error.
Therefore I suspect compiler optimization and it is too difficult for me to investiage C2000 assmeble codes.
So I post this issue to need your support.

>Put the code in the form you want me to investigate.

>Then for that source file, please follow the directions in the article How to Submit a Compiler Test Case.

I understand. I'll prepare codes to investigate this issue.

I'll notify this issue after I put our sources.

Best regards,

Hidehiko

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TMS320F28388D: Input parameters of subroutine are wrong optimized.