TMS320F28388D: regarding EMIF clock configuration and SDRAM clock

Part Number: TMS320F28388D

Hello

I am storing ADC results values using DMA through EMIF to SDRAM.

EMIF1 grabing in CPU1 to store 0x00 values in SDRAM and EMIF1 grabing in CPU2 storing differential ADC values using DMA to SDRAM

I am probing EMIF clock (which is going to SDRAM)which is configureed as follows

                            //
                           // Configure to run EMIF1 on half Rate (EMIF1CLK = CPU1SYSCLK/2).
                           //
                            SysCtl_setEMIF1ClockDivider(SYSCTL_EMIF1CLK_DIV_2);

But  not able to see clock signals in oscilloscope

What can be the issue not able to see clock signals in oscilloscope.

I have one confusion here as configuring EMIF clock means same clock signal will be given to SDRAM as SDRAM clock  or both are different signals?

Thanks in Advance