As the title says I can't get CAN to work with F28035 and USB docking station. I have tried the example ECanBack2Back from control suite and it always stucks to wait ACK. I'm not sure if it should send something to CANTX pin but I can't see anything there (I also tried with STM=0). I also have USB-CAN monitor and I have tried to get that to work but I can't get F28035 to send a single bit out. Please give me a starting point where to look for the failure.
Here is my initialization for the CAN in my own code:
struct ECAN_REGS ECanaShadow;
void ConfigureECan(void) // Initialize eCAN module
{
EALLOW; // EALLOW enables access to protected bits
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // 0=GPIO30 1=CANRXA 2=rsvd 3=rsvd
GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; // Asynch qual for GPIO30 (CANRXA)
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // 0=GPIO31 1=CANTXA 2=rsvd 3=rsvd//--- Configure eCAN RX and TX pins for CAN operation using eCAN regs ---//
ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
ECanaShadow.CANTIOC.bit.TXFUNC = 1;
ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;
ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
ECanaShadow.CANRIOC.bit.RXFUNC = 1;
ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;
//--- Configure bit timing parameters for eCANA ---//
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
// Wait until the CPU has been granted permission to change the configuration registers
do
{
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set..
ECanaShadow.CANBTC.all = 0;
ECanaShadow.CANBTC.bit.BRPREG = BRP_VAL; // Bit rate
ECanaShadow.CANBTC.bit.TSEG2REG = 12; // TSEG1 = 13 TQ
ECanaShadow.CANBTC.bit.TSEG1REG = 5; // TSEG2 = 6 TQ
ECanaShadow.CANBTC.bit.SJWREG = 3; // SJW = 3 TQ
ECanaShadow.CANBTC.bit.SAM = 1;
ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 0; // Set CCR = 0
ECanaShadow.CANMC.bit.PDR = 0;
ECanaShadow.CANMC.bit.DBO = 1; // Bytes MDH:7,6,5,4 MDL:3,2,1,0
ECanaShadow.CANMC.bit.WUBA = 0;
ECanaShadow.CANMC.bit.CDR = 0;
ECanaShadow.CANMC.bit.ABO = 0;
ECanaShadow.CANMC.bit.STM = 0;
ECanaShadow.CANMC.bit.MBNR = 0;
ECanaShadow.CANMC.bit.SCB = 0;
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
// Initialize all bits of 'Message Control Register' to zero
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero
ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
// as a matter of precaution.
ECanaRegs.CANTA.all = 0xFFFFFFFF; // Clear all TAn bits
ECanaRegs.CANRMP.all = 0xFFFFFFFF; // Clear all RMPn bits
ECanaRegs.CANGIF0.all = 0xFFFFFFFF; // Clear all interrupt flag bits
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
// Wait until the CPU no longer has permission to change the configuration registers
do
{
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared..
EDIS;
}
void InitECan(void)
{
ConfigureECan();
//--- Initialize mailboxes ---//
ECanaRegs.CANME.all = 0; // Disable all Mailboxes. Required before writing the MSGIDs
//--- Receive mailboxes ---//
ECanaMboxes.MBOX0.MSGID.all = 0x60L << 18;
ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
ECanaShadow.CANMD.bit.MD0 = 1; // configure as Receive mailbox
ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;
ECanaShadow.CANME.all = ECanaRegs.CANME.all;
ECanaShadow.CANME.bit.ME0 = 1;
ECanaRegs.CANME.all = ECanaShadow.CANME.all;
//--- Transmit mailboxes ---//
ECanaMboxes.MBOX1.MSGID.all = 0x161L << 18;
ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 1; // Send only 1 Byte
ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
ECanaShadow.CANMD.bit.MD1 = 0; // configure as Transmit mailbox
ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;
ECanaShadow.CANME.all = ECanaRegs.CANME.all;
ECanaShadow.CANME.bit.ME1 = 1;
ECanaRegs.CANME.all = ECanaShadow.CANME.all;
}
And a test sending which is done every 1 sec in main loop.:
ECanaMboxes.MBOX1.MDL.all = 0xAA000000;
ECanaMboxes.MBOX1.MDH.all = 0;
ECanaShadow.CANTRR.all = ECanaRegs.CANTRR.all;
ECanaShadow.CANTRR.bit.TRR1 = 1; // start transmission
ECanaRegs.CANTRR.all = ECanaShadow.CANTRR.all;
