Other Parts Discussed in Thread: TMDSCNCD28388D, C2000WARE
My customer uses two F28388D boards for FSI communication with DMA.
Communication works normally at 25MHz clock, but CLK and DATA signals are broken at 50MHz.
CLK = 50MHz

CLK = 25MHz

Both boards were connected to the same 3.3V and GND,
the master's TX was connected to the slave's RX through a buffer, and Master's RX was directly connected to the TX without a buffer.
And there is a 0 ohm resistor on the signal line.
Buffer is NC7WZ125 (OnSemi), and has propagation delay as below.

Are there any cautions when increasing the Clock?
Please let me know what to check.
