TMS320F28035 Trip zone issue

H Thomas,

Not sure if I understand your question correct: You ask why PWM ouput goes high when a trip occurs, right? If this is your question the answer is obvious - in the configuration you tell the Trip Module to force the PWMA and PWMB output high

Thomas Song said:

EPwm3Regs.TZCTL.bit.TZA = TZ_FORCE_HI;

By changeing it to TZ_FORCE_LO you tell the module to force the PWM outputs to a low state.

Thomas Song said:

Q2 : Could you inform me of how to enable PWM after a trip took place?

EALLOW;
EPwm1Regs.TZCLR.bit.OST = 1;
EDIS;

Best regards,

Andreas

Hi Andreas,

Thank you for your answer.

Sorry to make you confused, My problem is that the trip does not work properly.

The trip signal which goes to trip GPIO is toggling for some reason and also the PWM output signal also in synchronization with the trip signal. it seems like that trip occurs on falling edge and it releases on rising edge. I want to stop PWM output on first falling edge of the trip signal until I enable PWM output by software even though the trip signal is toggling.

According to the datasheet, it says that when using OST mode, the trip condition is latched, it means the PWM output will be disabled until I set the OST flag. But my case, even though I configure a trip as OST, the PWM output is still generating on rising edge of the trip signal and it works like periodic trip mode.

Do you have any idea about it?  Thanks for your help.

Best regards,

Thomas Song

Hi Thomas

When are you clearing the trip zone flag? Do you have trip interrupt routine? Once you clear one shot flag, you disable the trip module immediately.

It sound like when trip event happens, the MCU jumps to appropriate ISR, where you clear the OST flag (in order to go out from ISR without jumping immediately back) But the trip and interrupt logic are level triggered and not edge triggered. So if trip signal is still active (low) it will activate trip logic and ISR.

The way I handled this issue/feature is when I jup in trip ISR i manually disable PWM output through action qualifier/dead time module. Then I disable trip ISR and only after this I clear trip OST flag, and return from ISR.

Hope it makes sense

Mitja

Hi Thomas,

Based on your code sample the pin configured for asynchronous operation.  This is good since it eliminates input qualification delays.

The ePWM reference guide (sect 2.7.3) states that it takes (3) ePWM input clock cycles for a TZn low signal to latch the PWM trip states:

A minimum of 3*TBCLK low pulse width on TZn inputs is sufficient to trigger a fault condition on the ePWM module. If the pulse width is less than this, the trip condition may not be latched by CBC or OST latches. The asynchronous trip makes sure that if clocks are missing for any reason, the outputs can still be tripped by a valid event present on TZn inputs . The GPIOs or peripherals must be appropriately configured.

Does the input signal to the TZn pin stay low for more than (3) TBCLK cycles?

Jeff

Thomas,

Have you verified the OST is being detected by checking the TZFLG register?  I am not sure if those registers are EALLOW protected, but I would give that a try.