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TMS320F28386D: CM SSI communication receive unstable

Frederick LIN
Intellectual 600 points

Part Number: TMS320F28386D
Other Parts Discussed in Thread: C2000WARE

Hi,

I try to set the CM CLK as 125MHz and baudrate as 20MHz for the SPI Communication.

SSI_setConfig(base, ssiClk, protocol, mode, bitRate, dataWidth)

  • base = SSI0_BASE
  • ssiClk = 125000000
  • ProtocolMode = 3 ( Using comm. Mode3, means sample at positive edge and shifting bit at negative edge )
  • bitrate = 20000000
  • dataWidth = 8 bit

I notice that the SSI station can not get the value.

Here is how I test:

  1. Set the CM CLK as 120MHz, DSP sends a read command to a slave. SSI_readDataNonBlocking decodes and receive five RxData. It’s right.
  2. Set the CM CLK as 125MHz, DSP sends a read command to a slave. SSI_readDataNonBlocking decodes and receive only four RxData which is wrong, it should be received five RxData.

I try to check the real signal.

Note that

  • Ch1: CLK, Ch2: CS, Ch3: MOSI, Ch4: MISO

 

From the signal, We should get five RxData, but SSI_readDataNonBlocking just decodes four. We observed the SSISR Register, it response 0x19 ( SSI Busy bit ).

Is there any setting may cause this problem?

  • 0
    TI__Mastermind 30381 points

    Hello Frederick,

    Our subject matter expert on this peripheral is out of office. I may need to follow up with him on this particular issue you are seeing. 

    Since SSISR = 0x19, it indicates that the status bits are not behaving properly. For example, both transmit FIFO empty and transmit FIFO full are set. Since the SSI will take some cycles to transmit and receive data, is it possible for you try the SSI_writeData() and SSI_readData() functions rather than their _NonBlocking counterparts? These two functions will block until there is space in the TX FIFO and until there is a data on the RX FIFO.

    Can you also confirm that the CMCLK is configured for either 120MHz or 125MHz in your system? If you could please post the contents of the SSI registers, specifically the SSICR0 and SSICPSR.

  • 0 in reply to Gus Martinez
    Intellectual 600 points

    Hi Martinez,

    Although we call _NonBlocking, we have a while loop to call the SSI_readDataNonBlocking for timeout check.  So it is same as SSI_readData().

    We have confirmed that 120MHz or 125MHz correct. we enabled some the CM CPUTimer interrupt and the ISR trigger period is correct.

    SSI registers below,

    CMCLK 125 Mhz:

    SSI_0_CR0 = 711
    SSI_0_CPSR = 2

    the SSI Clock measured in scope is about 20.8MHz.



    ---
    CMCLK 120 Mhz:
    1. SSI_0_CR0 = 711
    2. SSI_0_CPSR = 2

    the SSI Clock measured in scope is about 20MHz.

  • 0 in reply to Frederick LIN
    TI__Mastermind 30381 points

    Hello,

    I'm checking with some colleagues. I will respond to you asap.

  • 0 in reply to Gus Martinez
    TI__Mastermind 30381 points

    Frederick,

    Frederick LIN said:
    Although we call _NonBlocking, we have a while loop to call the SSI_readDataNonBlocking for timeout check.  So it is same as SSI_readData().

    OK, I just want to make sure your code checks that there is data in the RX FIFO before reading the FIFO and that there is space in the TX FIFO before writing to the FIFO.

    Frederick LIN said:
    We have confirmed that 120MHz or 125MHz correct. we enabled some the CM CPUTimer interrupt and the ISR trigger period is correct.

    Thank you for this.

    What is the content of the SSISR *before* you start the transfers? 

    At this point, I'm still not sure what could be happening in your system. Is it possible for you to replicate this issue using one of the C2000ware SSI examples? There are a couple of loopback examples included which you can use.