TMS320F28388D: EMIF and SDRAM configuration

Hello

EMIF configuration is as follows 

void EMIF_Init(void)
{
uint16_t i;
EMIF_SyncConfig sdConfig;
EMIF_SyncTimingParams tParam;
//
// Configure to run EMIF1 on half Rate (EMIF1CLK = CPU1SYSCLK/2).
//
SysCtl_setEMIF1ClockDivider(SYSCTL_EMIF1CLK_DIV_2);

//
// Grab EMIF1 For CPU1.
//
EMIF_selectMaster(EMIF1CONFIG_BASE, EMIF_MASTER_CPU1_G);

//
// Disable Access Protection (CPU_FETCH/CPU_WR/DMA_WR).
//
EMIF_setAccessProtection(EMIF1CONFIG_BASE, 0x0);

//
// Commit the configuration related to protection. Till this bit remains
// set content of EMIF1ACCPROT0 register can't be changed.
//
EMIF_commitAccessConfig(EMIF1CONFIG_BASE);

//
// Lock the configuration so that EMIF1COMMIT register can't be changed
// any more.
//
EMIF_lockAccessConfig(EMIF1CONFIG_BASE);

setupEMIF1PinmuxSync16Bit();

//
// Configure SDRAM control registers. Needs to be
// programmed based on SDRAM Data-Sheet. For this example:
// T_RFC = 60ns = 0x6; T_RP = 18ns = 0x1;
// T_RCD = 18ns = 0x1; T_WR = 1CLK + 6 ns = 0x1;
// T_RAS = 42ns = 0x4; T_RC = 60ns = 0x6;
// T_RRD = 12ns = 0x1.
//
tParam.tRfc = 0x6U;
tParam.tRp = 0x1U;
tParam.tRcd = 0x1U;
tParam.tWr = 0x1U;
tParam.tRas = 0x4U;
tParam.tRc = 0x6U;
tParam.tRrd = 0x1U;
EMIF_setSyncTimingParams(EMIF1_BASE, &tParam);

//
// Configure Self Refresh exit timing.
// Txsr = 70ns = 0x7.
//
EMIF_setSyncSelfRefreshExitTmng(EMIF1_BASE, 0x7U);

//
// Configure Refresh Rate.
// Tref = 64ms for 8192 ROW, RR = 64000*100(Tfrq)/8192 = 781.25 (0x30E).
//
EMIF_setSyncRefreshRate(EMIF1_BASE, 781);

//
// Configure SDRAM parameters. PAGESIZE=2 (1024 elements per ROW),
// IBANK = 2 (4 BANK), CL = 3, NM = 1 (16bit).
//
sdConfig.casLatency = EMIF_SYNC_CAS_LAT_3;
sdConfig.iBank = EMIF_SYNC_BANK_4;
sdConfig.narrowMode = EMIF_SYNC_NARROW_MODE_TRUE;
sdConfig.pageSize = EMIF_SYNC_COLUMN_WIDTH_10;
EMIF_setSyncMemoryConfig(EMIF1_BASE, &sdConfig);

//
// Adding some delay.
//
for(i = 0; i < 12345; i++)
{
}
}

I am using the IS42S16320F SDRAM. The SDRAM data sheet says the following clock frequencies: 200, 166, 143 MHz. SDRAM works

but the EMIF configuration can be done only for 200MHz or 100MHz.

Whatever EMIF configuration we did above is correct or not?

Will, with a 100MHz or 200MHz EMIF configuration, data storage to SDRAM be possible?

Thanks in Advance