TMS320F28069M: Slow Adc Conversion

Ryan Laur

Hi,

I was trying to see how fast I could trigger the ADC interrupt with EPWM, and I am reaching a limit of about 700kHz, but it should go a bit higher. How can I increase this? I would specifically like to use the EPWM to easily change the sampling rate.

Here is my initialization code:

    EALLOW;

    SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
    SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1;

    AdcRegs.ADCCTL2.bit.CLKDIV4EN = 0;
    AdcRegs.ADCCTL2.bit.CLKDIV2EN = 0;
    AdcRegs.ADCCTL2.bit.ADCNONOVERLAP = 0; // Enable non-overlap mode    
    AdcRegs.ADCCTL1.bit.INTPULSEPOS	= 1;    
    AdcRegs.INTSEL1N2.bit.INT1E     = 1;  // Enabled ADCINT1
    AdcRegs.INTSEL1N2.bit.INT1CONT  = 0;  // Disable ADCINT1 Continuous mode    
    AdcRegs.INTSEL1N2.bit.INT1SEL 	= 0;    
    AdcRegs.ADCSOC0CTL.bit.CHSEL 	= 4;  // set SOC0 channel select to ADCINA4
    AdcRegs.ADCINTSOCSEL1.bit.SOC0 = 0;   
    AdcRegs.ADCSOC0CTL.bit.TRIGSEL 	= 5;   
    AdcRegs.ADCSOC0CTL.bit.ACQPS 	= 6;    

    EDIS;

    EPwm1Regs.TBCTL.bit.CLKDIV      = 0;
    EPwm1Regs.TBCTL.bit.HSPCLKDIV   = 0;
    EPwm1Regs.ETSEL.bit.SOCAEN	    = 1;		
    EPwm1Regs.ETSEL.bit.SOCASEL	    = 2;
    EPwm1Regs.ETPS.bit.SOCAPRD 	    = 1;		
    EPwm1Regs.TBPRD 			    = 0x02;	
    EPwm1Regs.TBCTL.bit.CTRMODE     = TB_COUNT_UP;
    EPwm1Regs.TBCTL.bit.HSPCLKDIV   = TB_DIV1;
    EPwm1Regs.TBCTL.bit.CLKDIV      = TB_DIV1;

    EALLOW;
    SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
    EDIS;

    while(1);
}

__interrupt void
adc_isr(void)
{
   GpioDataRegs.GPADAT.bit.GPIO12 = 0;

   AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; 
   PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;  

   GpioDataRegs.GPADAT.bit.GPIO12 = 0;
}

Thanks,

Ryan

over 3 years ago

0 Marlyn Rosales Castaneda20 over 3 years ago

TI__Mastermind 26900 points

Hi Ryan,

Ryan Laur said:
How can I increase this?

You would have to change the EPWM frequency, this is done through the TBPRD register.

More information is here about choosing the correct TBPRD value based on the desired frequency: https://training.ti.com/c2000-enhanced-pulse-width-modulator-epwm-time-base-submodule

Best Regards,

Marlyn

0 Ryan Laur over 3 years ago in reply to Marlyn Rosales Castaneda20

Prodigy 90 points

I think you misunderstood my question.

If you look at the above code, the period is set as fast as it can go. The maximum frequency attainable is 700khz.

Thanks,

Ryan

0 Marlyn Rosales Castaneda20 over 3 years ago in reply to Ryan Laur

TI__Mastermind 26900 points

Ryan,

Can you please setup AQ settings for the EPWM module and scope the output to check what frequency your EPWM is?

Best Regards,

Marlyn

0 Ryan Laur over 3 years ago in reply to Marlyn Rosales Castaneda20

Prodigy 90 points

Yes, I will try that and get back to you. Which module specifically?

0 Marlyn Rosales Castaneda20 over 3 years ago in reply to Ryan Laur

TI__Mastermind 26900 points

Hi Ryan,

This should be a simple addition to the code you have. For example reference the code below. You just need to setup a compare value and action qualifier events. After this you should be able to monitor EPWM1A.

  EPwm1Regs.TBPRD                 = 0xFFFF;   // Set period for ePWM1
  EPwm1Regs.CMPA.half.CMPA    = 0x0080;       // Set compare A value
  EPwm1Regs.AQCTLA.bit.CAU = 2;  // Set ouptut high
  EPwm1Regs.AQCTLA.bit.ZRO = 1;  // Set output low

Best Regards,

Marlyn

0 Ryan Laur over 3 years ago in reply to Marlyn Rosales Castaneda20

Prodigy 90 points

Ok, I put the AQC as fast as possible, and I get 45Mhz. So the EPWM is not the issue, it is the SOC of the ADC I would assume. Any thoughts?

0 Marlyn Rosales Castaneda20 over 3 years ago in reply to Ryan Laur

TI__Mastermind 26900 points

Ryan,

Could you please try toggling the GPIO upon entry of the ISR instead of setting it then clearing it within the ISR?

Best Regards,

Marlyn

0 Ryan Laur over 3 years ago in reply to Marlyn Rosales Castaneda20

Prodigy 90 points

So Right now the EPWM is set to 1 Mhz. Toggling the GPIO Triggers at the speed it was before, divided by 2. My maximum Rate is about 772khz. Toggling the GPIO upon entry to the ISR results in a rate of 386kHz, as expected.

From the rise of EPWM1 (CPMA) to the rise of the GPIO, it is about 440 ns, which is expected. As soon as I go past this ~772 kHz with the EPWM, the ISR doesn't trigger any faster.

0 Marlyn Rosales Castaneda20 over 3 years ago in reply to Ryan Laur

TI__Mastermind 26900 points

Hi Ryan,

The limiting factor here is not the EPWM frequency, but rather the ADC and the time it takes to branch to the ISR, execute the content in the ISR, and then branch back. Even if the EPWM is triggering as fast as it can, the timing it takes for the ADC to sample and perform the conversion + the ISR timings will be fixed.

Best Regards,

Marlyn

0 Ryan Laur over 3 years ago in reply to Marlyn Rosales Castaneda20

Prodigy 90 points

The ADC has the capability to sample at 3.46MSPS. If there is no code inside the ISR except for a gpio toggle, I should be able to exceed 1Mhz. According to other articles, it is possible. Would you be able refer me to a colleague that is knowledgeable on the issue?

Thank you,

Ryan

0 Marlyn Rosales Castaneda20 over 3 years ago in reply to Ryan Laur

TI__Mastermind 26900 points

Ryan,

Could you please try changing the INTPULSEPOS to 0 (INT pulse generation occurs when ADC begins conversion)? This should help overlap the end of the conversion time with the ISR context switch. Also, do you see any of the overflow flags being set (ADCINTOVF register)?

Best Regards,

Marlyn

0 Ryan Laur over 3 years ago in reply to Marlyn Rosales Castaneda20

Prodigy 90 points

The overlap is already set to 0, but I’ll check the overflow, thanks.

0 Ryan Laur over 3 years ago in reply to Marlyn Rosales Castaneda20

Prodigy 90 points

So the INTPULSEPOS is already set to 0. The overflow flag is getting set, but if I clear it, it doesn't make a difference.

Even with DMA transferring into a buffer, with the ADC in continuous mode (don't have to reset flag), I am still getting the same speed-cap.

0 Marlyn Rosales Castaneda20 over 3 years ago in reply to Ryan Laur

TI__Mastermind 26900 points

Hi Ryan,

Thank you for checking those settings. Just to confirm, your device is running at 90MHz, correct? Note that the ADC has a max operating frequency of 45MHz. Within your initialization both CLKDIV4EN and CLKDIV2EN are set to 0. If your device is running at 90MHz then you should configure the ADC to operate at 45MHz, otherwise we do not guarantee the behavior of the ADC. Is this something you could please change within your application if it applies before we proceed?

Best Regards,

Marlyn

0 Ryan Laur over 3 years ago in reply to Marlyn Rosales Castaneda20

Prodigy 90 points

Yes the device is running at 90 Mhz. The ADC is configured with CLKDIV4EN and CLKDIV2EN set to 0 as shown in the above code from my first post. Thus, the ADC CLK should be operating at 45Mhz.

Thanks,

Ryan

0 Hareesh Janakiraman over 3 years ago in reply to Ryan Laur

TI__Guru* 95315 points

Ryan,

Marlyn is out of the office today and will respond when she is back tomorrow. Thank you for your patience and understanding.

0 Marlyn Rosales Castaneda20 over 3 years ago in reply to Ryan Laur

TI__Mastermind 26900 points

Ryan,

If both the CLKDIV2EN and CLKDIV4EN bits are set to 0 then the ADC will be configured to run at SYSCLK not SYSCLK/2.

Best Regards,

Marlyn

0 Ryan Laur over 3 years ago in reply to Marlyn Rosales Castaneda20

Prodigy 90 points

Sorry about that, I overlooked that I thought both 0's was SYSCLK/2. If I use SYSCLK/2,. then now my maximum frequency that is triggering is halved, at about 386kHz. Thoughts?

0 MatthewPate over 3 years ago in reply to Ryan Laur

TI__Guru* 84570 points

Ryan,

Since the overflow flag is set, it means that the ADC processed another conversion before we could clear the flag. This could mean that the ISR can't service quickly enough based on the ADC speed.

Can you attach you .map file from the project(this should get generated to the same directory as the .out file). I'd like to make sure where in memory the ADC ISR is executing.

Best,
Matthew

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TMS320F28069M: Slow Adc Conversion