tms320f28035 PWM TBCTR wrong operation

Ricardo,

It looks like you've gotten a lot of the steps complete for your project.  I assume that you have already done this, but can you confirm you have min/max limits on your controller?


Because you are doing a variable frequency converter, you will need to be very careful when you update the TBPRD value.  For instance, if the controller changes TBPRD to be lower than the current value in TBCTR, the PWM will count up to 32768, overflow, reset to 0 and count up to TBPRD.  This will cause issues on your board.

The way that I've gotten around this on some boards is by having two interrupts:

1. Driven by a CpuTimer or a spare PWM in which the control loop for the Resonant converter is run.
2. Driven by the zero event of the resonant converter's PWM module. Therefore this interrupt will be variable frequency.  This interrupt will update the PWM's TBPRD, CMPA and CMPB values.  Because this interrupt will occur early on, you can assume that the TBCTR will be less than TBPRD.

If you want, take a look at the documentation and code included with the recently released TMDSHVRESLLCKIT kit at http://www.ti.com/f28xkits.  This kit implements the scheme I summarized above.


Thank you,
Brett

Hi Bret, Ricardo

Isn't it easier just to enable shadowing of PRD and CMP registers?

Regards, Mitja

Mitja,

This is a great point.  In almost every case, enabling the shadow registers will resolve this type of issue.

However, in my resonant system and (from what I can tell) Ricardo's system as well, multiple PWM settings need to be changed each interrupt cycle.  For instance the TBPRD, CMPA and CMPB registers will need to be changed and they must be updated in the same cycle.  Even with the shadow registers enabled, there is no guarantee that all three settings will be changed by the ISR before the PWM timer resets to zero.  Making sure that the interrupt is synched with the PWM update cycle solves this.

In the resonant projects C2000 has been working on, we've implemented two interrupts (as I've mentioned above) as well as enabled shadowing.  With both of these, I have not observed any issues with timing, etc.


Ricardo,

From my understanding, if you're using a fixed frequency interrupt, shadow mode should resolve all issues but the one I mention above.   It will only happen rarely.

Thank you,
Brett

Brett, 

1- In my system the SOC event is trigged by EPWM3 (Half-Bridge) at compB = CMPA / 2 in order to sample the output voltage in the middle of ON TIME of Half-Bridge Switch.

2- the EOC event of ADC that is sampling the output voltage is the trigger for the CLA task where the control law 2p2z is implemented, so the CLA task runs at the same frequency of Half-Bridge between 80kHz and 250kHz.

3- the tasks performed by CLA task are:

- ADC update

- control law 2p2z

- PWM update.

I can ensure that in the worst case (highest operation frequency) all the tasks listed above are finished before the end of the current switching cycle, so in this case is ensured that TBPRD, CMPA and CMPB will be updated by the shadow register at TBCTR ZRO event in the next switching cycle. 

Do you agree?

I would like to have a confirmation from you about the shadow registers, I would like to know if there is a shadow register for DBRED, DBFED and TBPHS?

Thanks 

Ricardo

Ricardo,

Yes I agree.  The only real negative is that the control loop frequency is variable in your system.  I'm not a controls expert, but according to various people in my team, the control loop should be fixed.  Otherwise, the coefficients should change as the frequency changes.  Honestly, because the variable frequency control loop theory is still relatively new, you'll need to see what is required for your design and make sure they meet your specs either way.

Unfortunately, there are no shadow register for DBRED, DBFED or TBPHS.  All of these could or could not affect your performance.  You'll need to create and look at a timing diagram to see whether your software strategy will need to change to reduce the chance of issues.


Thank you,
Brett