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TMS320F280039C: ADCs are half of expected counts

Part Number: TMS320F280039C
Other Parts Discussed in Thread: SYSCONFIG

Hello, 

My ADCs are reading half of the expected counts. If I apply 1.5V to the ADC I get 1024 instead of 2048. I feel like I have the scaling wrong somewhere. 

I added this to my initialization since I saw SysConfig generated this for the demo projects.  

    // asysctl initialization
    // Disables the temperature sensor output to the ADC.
    ASysCtl_disableTemperatureSensor();
    // Set the analog voltage reference selection to internal.
    ASysCtl_setAnalogReferenceInternal( ASYSCTL_VREFHI );
    // Set the internal analog voltage reference selection to 1.65V.
    ASysCtl_setAnalogReference1P65( ASYSCTL_VREFHI );

I also have the voltage reference set to 3.3V as I want: 

    // Set ADC voltage ref
    ADC_setVREF(adcHandle[0], ADC_REFERENCE_INTERNAL, ADC_REFERENCE_3_3V);
    ADC_setVREF(adcHandle[1], ADC_REFERENCE_INTERNAL, ADC_REFERENCE_3_3V);
    ADC_setVREF(adcHandle[2], ADC_REFERENCE_INTERNAL, ADC_REFERENCE_3_3V);
    ADC_setOffsetTrimAll(ADC_REFERENCE_INTERNAL, ADC_REFERENCE_3_3V);

This is my ADC init code - 

void Setup_FastADC()
{
    // Select interrupt source - this will be the last sample converted and therefore trigger the interrupt 1
    ADC_setInterruptSource(ADCC_BASE, ADC_INT_NUMBER1, ADC_DCBUS_SOCNUM);

    // Setup ADCs for PhA - this is triggered based off of counter EPWM1 SOCA (setup below)
    // Sample window must be > 75ns per datasheet, > 90ns for AGPIO per datasheet (at least > 11 SYSCLK cycles to be safe - 91.3ns)
    // Sample window must also be as long as 1 ADC clock cycle (40ns) - input sample window in SysClk cycles (11 cycle = 91.3ns)
    ADC_setupSOC(ADC_PHA_I_BASE, ADC_PHA_I_SOCNUM, ADC_TRIGGER_EPWM1_SOCA, ADC_PHA_I_CHANNEL, ADC_SAMPLE_WINDOW);
    ADC_setInterruptSOCTrigger(ADC_PHA_I_BASE, ADC_PHA_I_SOCNUM, ADC_INT_SOC_TRIGGER_NONE);

    // Configuring PPB in case we have any calibration to do
    // Configure PPB to subtract out any offset
    // PPB is associated with ADCA_SOC1
//    ADC_setupPPB(ADC_PHA_I_BASE, ADC_PHA_I_PPBNUM, ADC_PHA_I_SOCNUM);
//
//    // Write 0 to PPB will disable PPB offset calibration (change 0 to the offset we want if we need)
//    ADC_setPPBCalibrationOffset(ADC_PHA_I_BASE, ADC_PHA_I_PPBNUM, 0);

    // Setup ADCs for PhB - this is triggered based off of counter EPWM1 SOCA (setup below)
    // Sample window must be > 75ns per datasheet, > 90ns for AGPIO per datasheet (at least > 11 SYSCLK cycles to be safe - 91.3ns)
    // Sample window must also be as long as 1 ADC clock cycle (40ns) - input sample window in SysClk cycles (11 cycle = 91.3ns)
    ADC_setupSOC(ADC_PHB_I_BASE, ADC_PHB_I_SOCNUM, ADC_TRIGGER_EPWM1_SOCA, ADC_PHB_I_CHANNEL, ADC_SAMPLE_WINDOW);
    ADC_setInterruptSOCTrigger(ADC_PHB_I_BASE, ADC_PHB_I_SOCNUM, ADC_INT_SOC_TRIGGER_NONE);

//    // Configuring PPB in case we have any calibration to do
//    // Configure PPB to subtract out any offset
//    // PPB is associated with ADCB_SOC1
//    ADC_setupPPB(ADC_PHB_I_BASE, ADC_PHB_I_PPBNUM, ADC_PHB_I_SOCNUM);
//
//    // Write 0 to PPB will disable PPB offset calibration (change 0 to the offset we want if we need)
//    ADC_setPPBCalibrationOffset(ADC_PHB_I_BASE, ADC_PHB_I_PPBNUM, 0);

    // Setup ADCs for PhC - this is triggered based off of counter EPWM1 SOCA (setup below)
    // Sample window must be > 75ns per datasheet, > 90ns for AGPIO per datasheet (at least > 11 SYSCLK cycles to be safe - 91.3ns)
    // Sample window must also be as long as 1 ADC clock cycle (40ns) - input sample window in SysClk cycles (11 cycle = 91.3ns)
    ADC_setupSOC(ADC_PHC_I_BASE, ADC_PHC_I_SOCNUM, ADC_TRIGGER_EPWM1_SOCA, ADC_PHC_I_CHANNEL, ADC_SAMPLE_WINDOW);
    ADC_setInterruptSOCTrigger(ADC_PHC_I_BASE, ADC_PHC_I_SOCNUM, ADC_INT_SOC_TRIGGER_NONE);

//    // Configuring PPB in case we have any calibration to do
//    // Configure PPB to subtract out any offset
//    // PPB is associated with ADCC_SOC1
//    ADC_setupPPB(ADC_PHC_I_BASE, ADC_PHC_I_PPBNUM, ADC_PHC_I_SOCNUM);
//
//    // Write 0 to PPB will disable PPB offset calibration (change 0 to the offset we want if we need)
//    ADC_setPPBCalibrationOffset(ADC_PHC_I_BASE, ADC_PHC_I_PPBNUM, 0);

    // If we need any more PBB's we can copy them from above
    // Setup DCLink sampling -> This will trigger interrupt
    ADC_setupSOC(ADC_DCBUS_BASE, ADC_DCBUS_SOCNUM, ADC_TRIGGER_EPWM1_SOCA, ADC_DCBUS_CHANNEL, ADC_SAMPLE_WINDOW);
    ADC_setInterruptSOCTrigger(ADC_DCBUS_BASE, ADC_DCBUS_SOCNUM, ADC_INT_SOC_TRIGGER_NONE);

}

void Init_ADC()
{
    // asysctl initialization
    // Disables the temperature sensor output to the ADC.
    ASysCtl_disableTemperatureSensor();
    // Set the analog voltage reference selection to internal.
    ASysCtl_setAnalogReferenceInternal( ASYSCTL_VREFHI );
    // Set the internal analog voltage reference selection to 1.65V.
    ASysCtl_setAnalogReference1P65( ASYSCTL_VREFHI );

    // Setup ADC
    // Three ADC modules in this device
    // initialize the ADC handles
    adcHandle[0] = ADCA_BASE;
    adcHandle[1] = ADCB_BASE;
    adcHandle[2] = ADCC_BASE;

    // initialize the ADC results
    adcResult[0] = ADCARESULT_BASE;
    adcResult[1] = ADCBRESULT_BASE;
    adcResult[2] = ADCCRESULT_BASE;

    // Set ADC voltage ref
    ADC_setVREF(adcHandle[0], ADC_REFERENCE_INTERNAL, ADC_REFERENCE_3_3V);
    ADC_setVREF(adcHandle[1], ADC_REFERENCE_INTERNAL, ADC_REFERENCE_3_3V);
    ADC_setVREF(adcHandle[2], ADC_REFERENCE_INTERNAL, ADC_REFERENCE_3_3V);
    ADC_setOffsetTrimAll(ADC_REFERENCE_INTERNAL, ADC_REFERENCE_3_3V);

    // Set main clock scaling factor (60MHz max clock for the ADC module)
    // ADC clock set up for 30 MHz
    ADC_setPrescaler(adcHandle[0], ADC_CLK_DIV_2_0);
    ADC_setPrescaler(adcHandle[1], ADC_CLK_DIV_2_0);
    ADC_setPrescaler(adcHandle[2], ADC_CLK_DIV_2_0);

    // Set the ADC interrupt pulse generation to end of conversion
    ADC_setInterruptPulseMode(adcHandle[0], ADC_PULSE_END_OF_CONV);
    ADC_setInterruptPulseMode(adcHandle[1], ADC_PULSE_END_OF_CONV);
    ADC_setInterruptPulseMode(adcHandle[2], ADC_PULSE_END_OF_CONV);

    // Disables SOC burst mode.
    ADC_disableBurstMode(adcHandle[0]);
    ADC_disableBurstMode(adcHandle[1]);
    ADC_disableBurstMode(adcHandle[2]);

    // Set priority of SOCs
    ADC_setSOCPriority(adcHandle[0], ADC_PRI_ALL_HIPRI);
    ADC_setSOCPriority(adcHandle[1], ADC_PRI_ALL_HIPRI);
    ADC_setSOCPriority(adcHandle[2], ADC_PRI_ALL_HIPRI);

    // Enable ADCs
    ADC_enableConverter(adcHandle[0]);
    ADC_enableConverter(adcHandle[1]);
    ADC_enableConverter(adcHandle[2]);

    // Delay to allow ADCs to power up
    SysCtl_delay(5000U);

    // Setup ADCs for fast samples - A, B, C, DC Link
    Setup_FastADC();

    // Init motor PWM to trigger ADC
    MotorPWM_Init();

    // Enable ADC interrupt - Enables ADC interrupts in group 1 - priority 12
    // Kicks off the fast thread
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);
    Interrupt_register(INT_ADCC1, &adcC1ISR); // register ISR
}

Thanks for the help!