TMS320F28379D: HRPWM with a down counter

Hi,

B R said:

(*ePWM[j]).AQCTLA.bit.CAU = AQ_SET;

What was the logic behind keeping the CAU bit at SET. I believe this should be replaced with CAD instead of CAU. Checking when counter equals to CMPA in down count mode and counter equals to zero will be the same instant. Please check by replacing CAU with CAD.

Thanks,
Aditya

Hello Aditya, This certainly helped to at least get some switching waveform but results are not meeting the expectations yet. I am working with ePWM3 and the code for configuration is as follows:

void HRPWM_Config(period)
{

    //
    // ePWM channel register configuration with HRPWM
    // ePWMxA / ePWMxB toggle low/high with MEP control on Rising edge
    //

        EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;  // set Shadow load
        EPwm3Regs.TBPRD = period-1;             // PWM frequency = 1 / period
        EPwm3Regs.CMPA.bit.CMPA = 0;   // set duty 0% initially
        EPwm3Regs.CMPA.bit.CMPAHR = (0 << 8);   // initialize HRPWM extension
        EPwm3Regs.CMPB.bit.CMPB = 0;   // set duty 0% initially
        EPwm3Regs.CMPB.all |= (0 << 8);         // initialize HRPWM extension
        EPwm3Regs.TBPHS.all = 0;
        EPwm3Regs.TBCTR = 0;

        EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN;
        EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE;
        EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
        EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
        EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
        EPwm3Regs.TBCTL.bit.FREE_SOFT = 0x11;

        EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;  // LOAD CMPA on CTR = 0
        EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
        EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
        EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;


        EPwm3Regs.AQCTLA.bit.ZRO = AQ_CLEAR;      // PWM toggle high/low
        EPwm3Regs.AQCTLA.bit.CAD = AQ_SET;
        EPwm3Regs.AQCTLB.bit.ZRO = AQ_CLEAR;
        EPwm3Regs.AQCTLB.bit.CBD = AQ_SET;


    EALLOW;

      EPwm3Regs.HRCNFG.all = 0x0;
      EPwm3Regs.HRCNFG.bit.EDGMODE = HR_REP;  // MEP control on rising edge
      EPwm3Regs.HRCNFG.bit.CTLMODE = HR_CMP; // CMPAHR controls the MEP
      EPwm3Regs.HRCNFG.bit.HRLOAD  = HR_CTR_ZERO;  // Shadow load on CTR=Zero
      EPwm3Regs.HRCNFG.bit.EDGMODEB = HR_REP;  // MEP control on rising edge
      EPwm3Regs.HRCNFG.bit.CTLMODEB = HR_CMP;
      EPwm3Regs.HRCNFG.bit.HRLOADB  = HR_CTR_ZERO;
      EPwm3Regs.HRCNFG.bit.SELOUTB  = HR_INVERT_B; // 1: ePWMxB output is inverted version of ePWMxA signal.
      #if(AUTOCONVERT)
      EPwm3Regs.HRCNFG.bit.AUTOCONV = 1;      // Enable auto-conversion
                                               // logic
      #endif
      EPwm3Regs.HRPCTL.bit.HRPE = 0; // Turn off high-resolution period
                                      // control.

   EDIS;


        // Interrupt where we will change the Compare Values
            //
            EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Zero event
            EPwm3Regs.ETSEL.bit.INTEN = 1;                // Enable INT
            EPwm3Regs.ETPS.bit.INTPRD = ET_3RD;           // Generate INT on 3rd event

}

The main problem is that duty cycle is not matching its set value that is controlled by the variable "input" in the following code. Here "DutyFineA" and "input" are of types Uint16 and float. The duty cycle of the switching waveforms remains same even when I changing the value of "input" that is varied in the range of 0.0f to 0.7f. I will appreciate all your help to find an issue with this code. 

        DutyFineA = _IQ15(input);
                    /* all below calculation apply for CMPB as well
                    // CMPA_reg_val , CMPA_reg_val is calculated as a Q0.
                    // Since DutyFine is a Q15 number, and the period is Q0
                    // the product is Q15. So to store as a Q0, we shift right
                    // 15 bits.

                    CMPA_reg_val = ((long)DutyFine * EPwm1Regs.TBPRD)>>15;

                    // This next step is to obtain the remainder which was
                    // truncated during our 15 bit shift above.
                    // compute the whole value, and then subtract CMPA_reg_val
                    // shifted LEFT 15 bits:
                    temp = ((long)DutyFine * EPwm1Regs.TBPRD) ;
                    temp = temp - ((long)CMPA_reg_val<<15);

                    ** If auto-conversion is disabled, the following step can be
                    // skipped. If autoconversion is enabled, the SFO function will
                    // write the MEP_ScaleFactor to the HRMSTEP register and the
                    // hardware will automatically scale the remainder in the CMPAHR
                    // register by the MEP_ScaleFactor.
                    // Because the remainder calculated above (temp) is in Q15 format,
                    // it must be shifted left by 1 to convert to Q16 format for the
                    // hardware to properly convert.
                    CMPAHR_reg_val = temp<<1;

                    ** If auto-conversion is enabled, the following step is performed
                       automatically in hardware and can be skipped
                    // This obtains the MEP count in digits, from
                    // 0,1, .... MEP_Scalefactor.
                    // 0x0080 (0.5 in Q8) is converted to 0.5 in Q15 by shifting left 7.
                    // This is added to fractional duty*MEP_SF product in order to round
                    // the decimal portion of the product up to the next integer if the
                    // decimal portion is >=0.5.
                    //
                    //Once again since this is Q15
                    // convert to Q0 by shifting:
                    CMPAHR_reg_val = (temp*MEP_ScaleFactor+(0x0080<<7))>>15;

                    ** If auto-conversion is enabled, the following step is performed
                       automatically in hardware and can be skipped
                    // Now the lower 8 bits contain the MEP count.
                    // Since the MEP count needs to be in the upper 8 bits of
                    // the 16 bit CMPAHR register, shift left by 8.
                    CMPAHR_reg_val = CMPAHR_reg_val << 8;

                    ** If auto-conversion is enabled, the following step is performed
                       automatically in hardware and can be skipped
                    // Add the offset and rounding
                    CMPAHR_reg_val += 0x0080;

                    // Write the values to the registers as one 32-bit or two 16-bits
                    EPwm1Regs.CMPA.bit.CMPA = CMPA_reg_val;
                    EPwm1Regs.CMPA.bit.CMPAHR = CMPAHR_reg_val;
                    */

                    //
                    // All the above operations may be condensed into
                    // the following form:
                    // EPWM1 calculations


         if(UpdateFine)
                         {
                                 CMPA_reg_val = ((long)DutyFineA * (EPwm3Regs.TBPRD)) >> 15;
                                 temp = ((long)DutyFineA * (EPwm3Regs.TBPRD)) ;
                                 temp = temp - ((long)CMPA_reg_val << 15);


                                #if(AUTOCONVERT)
                                 CMPAHR_reg_val = temp << 1; // convert to Q16

                                #else
                                 CMPAHR_reg_val = ((temp * MEP_ScaleFactor) +
                                                   (0x0080 << 7)) >> 15;
                                 CMPAHR_reg_val = CMPAHR_reg_val << 8;

                                #endif

                                //
                                // Example for a 32 bit write to CMPA:CMPAHR
                                //
                                 EPwm3Regs.CMPA.all = ((long)CMPA_reg_val) << 16 |
                                                       CMPAHR_reg_val; // loses lower 8-bits


                                 if (Reference==4 && duty_counter < 1000)
                                 {
                                     Duty_Capture[duty_counter] = EPwm3Regs.CMPA.all;
                                     Duty_Capture1[duty_counter] = _IQ16(input);
                                     duty_counter++;

                                 }

                         }
         //
                     // Call the scale factor optimizer lib function SFO()
                     // periodically to track for any change due to temp/voltage.
                     // This function generates MEP_ScaleFactor by running the
                     // MEP calibration module in the HRPWM logic. This scale
                     // factor can be used for all HRPWM channels. The SFO()
                     // function also updates the HRMSTEP register with the
                     // scale factor value.
                     //
                     status = SFO(); // in background, MEP calibration module
                                     // continuously updates MEP_ScaleFactor

                     if(status == SFO_ERROR)
                     {
                         error();   // SFO function returns 2 if an error occurs & #
                                    // of MEP steps/coarse step
                     }              // exceeds maximum of 255.

What is the duty that you see when you change values from 0 to 0.7?

Hi,

Thanks for sharing this. I need to get back and check the performance at lower duty cycle for down-count HRPWM.

The solution that you've done is really smart! Appreciate you for sharing the idea here.

Regards,

Aditya