TMS320F280025: PLL Reference Clock Lost Detection triggered, Missing-Clock-Detect not

Hi Quy,

Before going in to what may have caused MCD, can you please provide some details:

    - Clock source (external oscillator, crystal, internal oscillator, etc...).  If possible, provide input clock schematics if using external oscillator or crystal

    - PLL settings (clock multipliers and dividers)

Thanks and regards,

Joseph

Hi Joseph,

Thank you for your quick reply.

Sorry for the missunderstanding.As I mentioned in earlier post, we use PLL from clock source INTOSC2.

The MCD is not triggered. The PLL Reference Clock Lost Detection is triggered.

Please find below my code:

#define CPU_IMULT                   10uL                  /**< integer value of the multiplier */
#define CPU_REFDIV                  0uL                   /**< reference divider for the OSCCLK  */
#define CPU_ODIV                    0uL                   /**< output divider of the PLLRAWCLK */
#define CPU_PLLCLK_DIV_1            0u                    /**< PLLCLK_BY_1 SPRUIN7A, Table 3-50 */
#define CPU_PLLCLK_DIV              CPU_PLLCLK_DIV_1      /**< PLLSYSCLK = PLLRAWCLK */
#define CPU_OSC2                    0u    /**< OSCCLK = INTOSC2. SPRUIN7A, Table 3-44. */
/** TMS320F28002x has 224 Vector IDs. The first 3 initialized by Boot ROM */
#define CPU_NO_USED_VECTOR_ID       221u
/** SPRSP45B . Table 7-4. Minimum Required Flash Wait States */
#define CPU_MIN_WAIT_STATES         4u
/** PLL multipliers and dividers - 100Mhz clock */
#define CPU_SYS_PLL_MULT            ((u32)((CPU_REFDIV << 24u) | (CPU_ODIV << 16u) | CPU_IMULT))
/** 7.11.3.2.1.4 APLL Characteristics - SYS PLL Lock Time = 1024 OSCCLK * (REFDIV+1) */
#define CPU_LOCK_TIMEOUT            ((u32)(1024uL * (CPU_REFDIV + 1uL)))


void CPU_InitSysPll(void)
{
  u32 u32Timeout;
  u16 u16PllLockStatus;

  EALLOW;

  /* Bypass PLL and set dividers to /1 */
  ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0u;

  /* Delay at 200 OSCCLK cycles required post PLL bypass */
  CPU_Delay100Cycles();
  CPU_Delay100Cycles();

  /* Turn off the PLL */
  ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0u;

  /* Delay 100 OSCCLK cycles to wait for PLL turning off */
  CPU_Delay100Cycles();

  ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = CPU_OSC2;

  /* Delay of 300 OSCCLK cycles for the setting takes effect */
  CPU_Delay100Cycles();
  CPU_Delay100Cycles();
  CPU_Delay100Cycles();

  /* Set dividers to /1 to ensure the fastest PLL configuration */
  ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = CPU_PLLCLK_DIV_1;

  /* Program PLL multipliers */
  ClkCfgRegs.SYSPLLMULT.all = CPU_SYS_PLL_MULT;

  /* Enable SYSPLL */
  ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 1u;

  u32Timeout = CPU_LOCK_TIMEOUT;
  u16PllLockStatus = ClkCfgRegs.SYSPLLSTS.bit.LOCKS;

  /* Wait for the SYSPLL lock */
  while((u16PllLockStatus != 1u) && (u32Timeout != 0uL))
  {
    u16PllLockStatus = ClkCfgRegs.SYSPLLSTS.bit.LOCKS;
    u32Timeout--;
  }

  /* Set divider to produce slower output frequency to limit current increase */
  ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = CPU_PLLCLK_DIV + 1u;

  /* Enable PLLSYSCLK is fed from system PLL clock */
  ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1u;

  /* Delay 100 OSCCLK cycles for the setting takes effect */
  CPU_Delay100Cycles();

  /* Set the divider to user value */
  ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = CPU_PLLCLK_DIV;
  EDIS;
}

Regards,

Quy

Hi Quy,

Sorry, missed those details especially the last word in your problem statement.  Anyway, looking at your code settings, i see that IMULT is 10 and all dividers are set to 1.  INTOSC2 produces 10MHz and multiplied by IMULT, this produces a VCO clock of 10MHz*10 or 100MHz.  This is way too low for the PLL to operate.  Please refer to table 7.11.3.2.1.6 on Internal Clock Frequencies f(VCOCLK) range is from 220Mhz to 600MHz.  To have the best performance, set the VCO to nominal, or mid value which is around 400MHz.  Set IMULT to 40 then set PLL divider to 2 and finally set SYSCLK divider to 2 to get to 100MHz SYSCLK.

The 100MHz VCO clock  is the most probable reason for having PLL reference clock lost. Give this a try and let me know how it works.

Regards,

Joseph

Hi Joseph,

Thank you for the reply.

I changed the SW as your suggestion.

The faulty devices triggered the reset faster (before changing each 2-3minutes, after changing each second)

The faulless devices trigger always no reset.

#define CPU_IMULT                   40uL                  /**< integer value of the multiplier */
#define CPU_REFDIV                  0uL                   /**< reference divider for the OSCCLK  */
#define CPU_ODIV                    1uL                   /**< output divider of the PLLRAWCLK */
#define CPU_PLLCLK_DIV_1            0u                    /**< PLLCLK_BY_1 SPRUIN7A, Table 3-50 */
#define CPU_PLLCLK_DIV_2            1u                    /**< PLLCLK_BY_2 SPRUIN7A, Table 3-50 */
#define CPU_PLLCLK_DIV              CPU_PLLCLK_DIV_2      /**< PLLSYSCLK = PLLRAWCLK */

I also tried with other settings and we have the same behaviour

#define CPU_IMULT                   40uL                  /**< integer value of the multiplier */
#define CPU_REFDIV                  0uL                   /**< reference divider for the OSCCLK  */
#define CPU_ODIV                    3uL                   /**< output divider of the PLLRAWCLK */
#define CPU_PLLCLK_DIV_1            0u                    /**< PLLCLK_BY_1 SPRUIN7A, Table 3-50 */
#define CPU_PLLCLK_DIV              CPU_PLLCLK_DIV_1      /**< PLLSYSCLK = PLLRAWCLK */

Regards,

Quy

Hi Quy,

I don't see anything wrong with your PLL setup routine but just to be sure, can you take a snapshot of the register display like below:

I see you have replicated the PLL setting function of the driverlib function.  The above setting is what I am reading with using INTOSC2, IMULT=40, REFDIV=0,  ODIV=2 and SYSCLKDIV = 2.  I'm using above clock settings on a couple of parts, running then for a long time and do not see the DCC issue you were reporting using the driverlib function SysCtl_setClock.  Let's check first to see if the clock registers are populated correctly.

Best regards,

Joseph

Hi Jospeh,

I'd like to clarify again. We want to use 3 algoriths for clock monitoring

• with MDC
• with PLL Reference Clock Lost Detection
• with DCC

We don't see issues with MDC or DCC as you. We have only problem with PLL Reference Clock Lost Detection.

We think your suggestion for the settings make sense. We set now the frequences in middle of allowed range.

I have 2 SWs with the same settings REFDIV = 0, IMULT = 40, ODIV = 3, SYSCLKDIVSEL = 0 (we'd like simple setting in DCC so wer set Fclk1 = Fsysclk with SYSCLKDIVSEL = 0)

• SW1: with "ClkCfgRegs.MCDCR.bit.SYSREF_LOST_MCD_EN = 1"
• SW2: without "ClkCfgRegs.MCDCR.bit.SYSREF_LOST_MCD_EN = 1

As soon as SW1 is in the device, I cannot connect with it using debugger (XDS200). Please find attached the message

We have to flash SW2 via LIN Bootloader. As soon as SW2 is in the device, I can connect with debugger and read the registers:

If I flash SW1 again, I cannot connect with it using debugger (XDS200) again.

Regards,

Quy

Hi Quy,

Sorry, I have trouble understanding what the actual issue that causes the loss of connection to the debugger.  Can you use the PLL setup routines in driverlib (SysCtl_setClock) instead?  There are PLL / DCC setup and timing step sequences that need to be followed in the PLL setup and might have been missed in your routine.

Thanks,

Joseph

Hi Quy,

In addition, can you show where SYSREF_LOST_MCD is being set in your code when this is used?

Joseph

Hi Quy,

As to the question whether ClkCfgRegs.MCDCR.bit.SYSREF_LOST_MCD_EN is required or not, you can remove this from your code since DCC check as well as MCD already covers the functionality of SYSREF_LOST_MCD_EN.

Regards,

Joseph

Hi Joseph,

We cannot use the PLL setup routine in driverlib because we don't use driverlib, we just use the library from device_support. Our code however replicates the code in f28002x_sysctrl.c. For the delay we just use

static void CPU_Delay100Cycles(void)
{
  /* repeat NOP 100 times */
  __asm(" RPT #100 || NOP");
}

About SYSREF_LOST_MCD,

• we set up PLL first
• then perform some internal tests (RAM, register, ...)
• then copy ram functions (replicate function in driverlib)
• init flash (replicate function in driverlib)
• init PieCtrl and InitPieVectTable (replicate function in driverlib)
• then enable MCD (just to be sure)
• then turn on SYSREF_LOST_MCD

• static void MCU_ClockMissingDetectionEnable(void)
  {
    EALLOW;
    /* Enable the missing clock detection (MCD) Logic as a precaution */
    ClkCfgRegs.MCDCR.bit.MCLKOFF = 0u;
    /* enable Reference Clock Lost to trigger a CLOCKFAIL event */
    ClkCfgRegs.MCDCR.bit.SYSREF_LOST_MCD_EN = 1u;
    EDIS;
  }

• then setup DCC

Regards,

Quy