TMS320F280025: CMPSS does not detect a pulse width with 3.7us

Hung Kai Woo1

My project is using cmpss module 4 to detect pulse with width ~ 3.5-3.7us max voltage is 3.3V with below code

    CMPSS_enableModule(PLC_CMPSS_BASE);
    ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_4,4U);
    CMPSS_configHighComparator(CMPSS4_BASE, CMPSS_INSRC_DAC);
    CMPSS_configDAC(CMPSS4_BASE, CMPSS_DACREF_VDAC | CMPSS_DACVAL_SYSCLK |
                    CMPSS_DACSRC_SHDW);
    CMPSS_setDACValueHigh(CMPSS4_BASE, 4000);

        //
        // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
        // the asynchronous comparator output.
        //
    CMPSS_configOutputsHigh(CMPSS4_BASE, CMPSS_TRIP_ASYNC_COMP |
                            CMPSS_TRIPOUT_ASYNC_COMP|CMPSS_TRIPOUT_LATCH);

In main.c loop, I am using below code to check the status of CMPSS4

            while((CMPSS_getStatus(CMPSS4_BASE) & CMPSS_STS_HI_LATCHFILTOUT) != 0U)
            {
                ;
            }

However, the CMPSS_getStatus() always return 0. I have done some test. 1 is return using the function if the signal is 0 to 3.3V and keep 3.3V.

My question is that does CMPSS does not detected pulse width is too small in term micro second

Is it turn or I make a mistake.

HK Woo

over 4 years ago

0 MatthewPate over 4 years ago

TI__Guru* 85960 points

HK,

While there will be some delay in the path due to system clock cycles, you are correct that we should definitely see a 3.7us pulse get detected.

Can you check the status of the COMPSTSCLR(HSYNCCLKEN) bit and make sure it is set to "0". This disables the ePWM from auto clearing the latch each PWM period. I assuming all the filter settings are "0" so there is not qualification of the signal from the COMPH.

Best,

Matthew

0 Hung Kai Woo1 over 4 years ago in reply to MatthewPate

Intellectual 825 points

1. Cannot find a bit call HSYNCCLKEN under COMPSTSCLR. Please find screen capture below

2. How to check filter qualification of the signal.

0 MatthewPate over 4 years ago in reply to Hung Kai Woo1

TI__Guru* 85960 points

Hung,

I mis-typed the register, the HSYNCCLREN is the correct bit, and it is disabled as we want it.

The filter settings are in CTRIPHFILCTL and CTRIPHFILCLKCTL. Make sure everything is 0 for no extra filtering.

Also, I'm assuming your SYSCLK is 100MHz, but please let me know if otherwise.

Best,

Matthew

0 Hung Kai Woo1 over 4 years ago in reply to MatthewPate

Intellectual 825 points

Matthew

Do you mean HSYNCCLEREN need to be 1?

Please find filter setting screen shot below

0 MatthewPate over 4 years ago in reply to Hung Kai Woo1

TI__Guru* 85960 points

Hung,

No, we want to keep HSYNCCLKEN = 0 as you have it. And all the filter settings are 0, which would mean no extra filters applied to the signal.

Can you send me your Clock Configuration settings(PLLCR, etc)

Best,
Matthew

0 Hung Kai Woo1 over 4 years ago in reply to MatthewPate

Intellectual 825 points

Please advise how to check it.

In my code. I use SysCtl_setClock(DEVICE_SETCLOCK_CFG);

0 MatthewPate over 4 years ago in reply to Hung Kai Woo1

TI__Guru* 85960 points

Hung,
Apologies, can you also give the value for your external Crystal(XTAL) on the board.

Based on the above your system will be running at ((XTAL/3)*(30/4))/2

Whatever we get for the system clock period will determine the pulse width of the COMP we can detect/latch.

Best,

Matthew

0 Hung Kai Woo1 over 4 years ago in reply to MatthewPate

Intellectual 825 points

20M crystal

0 MatthewPate over 4 years ago in reply to Hung Kai Woo1

TI__Guru* 85960 points

Hung,

So, our SysClk is at 25MHz which will mean that the latched path will need a threshold break even of at least 2 SYSCLKs to latch the signal or 2 * 40ns = 80ns. So we should be more than fine here for a 3.7us event.

Let me ask some others on the team to take a look; I can't give any reason this should not be working.

Best,

Matthew

0 Hung Kai Woo1 over 4 years ago in reply to MatthewPate

Intellectual 825 points

Any updated?

0 MatthewPate over 4 years ago in reply to Hung Kai Woo1

TI__Guru* 85960 points

Hung,

Can we try and not use the latched version of the output, i.e. send the ASYNC or just SYNC signal to the CTRIP path to the PWM, and monitor that behavior?

I'm not certain that the final CMPSS_TRIPOUT_LATCH or'd to these signals is valid for the CMPSS_configOutputsHigh as well.

CMPSS_configOutputsHigh(CMPSS4_BASE, CMPSS_TRIP_ASYNC_COMP |
CMPSS_TRIPOUT_ASYNC_COMP|CMPSS_TRIPOUT_LATCH);

Best,

Matthew

0 Hung Kai Woo1 over 4 years ago in reply to MatthewPate

Intellectual 825 points

Same result

0 Marlyn Rosales Castaneda20 over 4 years ago in reply to Hung Kai Woo1

TI__Mastermind 27200 points

Hi Hung,

Would you be able to provide a scope capture of your input signal and the comparator output (CTRIPOUT)? I would like to make sure that it is indeed missed and its not just a software issue.

Hung Kai Woo1 said:
1 is return using the function if the signal is 0 to 3.3V and keep 3.3V.

Do you mean that for a constant voltage above your DAC value it will output a 1 or that only a constant 3.3V will result in an output of 1?

Hung Kai Woo1 said:
CMPSS_setDACValueHigh(CMPSS4_BASE, 4000);

What voltage does 4000 correspond to in your application? It looks like you have configured VDAC as the reference voltage.

Best Regards,

Marlyn

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TMS320F280025: CMPSS does not detect a pulse width with 3.7us