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TMS320F28388D: Interrupt mode in enet_lwip example

Part Number: TMS320F28388D

Hello there,

In the enet_lwip example, in the Ethernet_init() function I see this line:

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pInitCfg->dmaMode.InterruptMode = ETHERNET_DMA_MODE_INTM_MODE2;
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This sets the INTM field (interrupt mode) field in the DMA_Mode register to 2. What is the reason for this? By default it is set to 1 in Ethernet_getInitConfig() in ethernet.c.
Furthermore when I look at the Ethernet_genericISR() code, I see a comment "This assumes the INTM interrupt mode 1". Why?

Can you explain in what kind of application I would choose INTM 0, 1, or 2? I read the description in the TRM (Table 43-322), but I don't understand the practical implications. It refers to table "DWC_ether_qos Transfer Complete Interrupt Behavior" but I can't find that one.

Thanks and kind regards,
Arjan

  • Arjan,

    Will take a look at the TRM and get back to you,

    Best Regards

    Siddharth

  • Hi Siddharth,

    Did you get a chance to check the TRM?

    Thanks,
    Arjan

  • Arjan, 

    Agree that the TRM is not very clear about it and it references some configuration from the design doc .

    The "DWC_ether_qos Transfer Complete Interrupt Behavior" table is part of the design doc and  it mentions about the behavior of the Transmit Per Channel Interrupt , Receive Per Channel Interrupt and Common Interrupt based on the value configured for INTM.

    1) INTM =0  - A pulse is asserted on these output signals when corresponding TX/RX transfer complete event is detected.

    2) INTM =1 - This reflect the value of corresponding TI/RI bits in DMA_CH[n]_Status register when the corresponding interrupt enable is set

    3) INTM =2 - In this mode, RI/TI interrupts are queued, if another TI/RI event(s) is detected before the TI/RI bits are cleared forthe previous event ,it is set
    again.

    Hope this helps.  

    Best Regards

    Siddharth