TMS320F28388D: IPC between different core

2021 Byron

Part Number: TMS320F28388D

Hi, the kidness engineer of TI's company.

like the example above, without any ISR, I am curious about how to make sure no conflict between different core in 28388d ?

s.t. if CPU1 write data to this msgram "MSGRAM_CPU_TO_CM_ECAT" while the CM core read the value in this ram at the same time,

how to make sure cpu1 is finish the writing before cm read, if without any isr?

over 3 years ago

+1 Manoj Santha Mohan over 3 years ago

TI__Guru 55700 points

Byron,

Using ISR is the most efficient method. If for some reason you don't want to use ISR, you can use IPC_sync to synchronize both the cores. But, use polling of IPC flag to synchronize the cores.

In CPU1 after you had written to msgram MSGRAM_CPU_TO_CM_ECAT, use IPC_sync function. In CM side of code, before you read make sure to use IPC_sync function. This will ensure CM doesn't read MSGRAM_CPU_TO_CM_ECAT before CPU1 finishes writing.

Regards,

Manoj

+1 2021 Byron over 3 years ago in reply to Manoj Santha Mohan

Prodigy 20 points

Thanks, Manoj

It's really help me a lot.

so, if i don't use ISR or IPC_sync function, some err may happening when one cpu is writing while another is reading, am i right?

0 Manoj Santha Mohan over 3 years ago in reply to 2021 Byron

TI__Guru 55700 points

2021 Byron said:
so, if i don't use ISR or IPC_sync function, some err may happening when one cpu is writing while another is reading, am i right?

Yes, that's correct

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TMS320F28388D: IPC between different core