Part Number: TMS320F280039C
In the Tech Ref, SPRUIW9A – OCTOBER 2021 – REVISED MARCH 2022...
Page 3002 it states:
A programmable baud generator produces a baud clock scaled from the input clock VCLK
Page 3003 is a diagram with VCLK feeding into the SCIBAUD register.
BUT, where is VCLK coming from? I have grepped the whole document for the term VCLK and have not found a clock-tree diagram that shows where VCLK comes from.
Is there a master clock-tree diagram available that shows VCLK exiting a module (the VCLK src)?
