According to the Technical Reference, SPRUIW9A – OCTOBER 2021 – REVISED MARCH 2022, page 3076, SCIFLR register, Parity bit:
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Parity error flag.
This bit is effective in LIN or SCI-compatible mode. This bit is setwhen a parity error is detected in the received data. In SCI addressbitmode, the parity is calculated on the data and address bit fieldsof the received frame. In idle-line mode, only the data is used tocalculate parity. An error is generated when a character is receivedwith a mismatch between the number of 1s and its parity bit. Formore information on parity checking, see the "SCI Global ControlRegister (SCIGCR1)" description. If the parity function is disabled(that is, SCIGCR1.2 = 0), the PE flag is disabled and read as 0.Detection of a parity error causes the LIN to generate an errorinterrupt if the SET PE INT bit = 1.
This bit is cleared by:
- Reading the corresponding interrupt offset in the SCIINTVECT0/1 register
- Setting the SWnRESET bit (SCIGCR1.7)
- RESET bit (SCIGCR0.0)
- System reset
- Reception of a new charcter (SCI-compatible mode) or frame (LIN mode)
- Writing a 1 to this bit
Reset type: SYSRSn
0h (R/W) = No parity error or parity disabled.
1h (R/W) = Parity error detected.
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However, I have parity disabled but still find the value '1' in the PE flag. See attached images...
