TMS320F28075: 60MHz configuration worked?

EUN WOO LEE82

Part Number: TMS320F28075
Other Parts Discussed in Thread: C2000WARE

I made a control board with TMS320F28075. And with PLL, the CPU brings up in 80MH, 100MHz, 120MHz. But, strangely, it does not boot up in 60MHz settings.

Here is my code.

//*****************************************************************************
//
// Defines related to clock configuration
//
//*****************************************************************************
//
// 20MHz XTAL on controlCARD. For use with SysCtl_getClock().
//
#define DEVICE_OSCSRC_FREQ 20000000U

//
// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
// PLLSYSCLK = 20MHz (XTAL_OSC) * 10 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2)
//
#if defined(SYSTEM_CLK_120MHz)
#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(12) | \
SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \
SYSCTL_PLL_ENABLE)
#elif defined(SYSTEM_CLK_100MHz)
#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(10) | \
SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \
SYSCTL_PLL_ENABLE)
#elif defined(SYSTEM_CLK_80MHz)
#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(8) | \
SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \
SYSCTL_PLL_ENABLE)
#elif defined(SYSTEM_CLK_60MHz)
#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(6) | \
SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \
SYSCTL_PLL_ENABLE)
#endif
//
// 100MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the
// code below if a different clock configuration is used!
//
#if defined(SYSTEM_CLK_120MHz)
#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 12 * 1) / 2)
#elif defined(SYSTEM_CLK_100MHz)
#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 10 * 1) / 2)
#elif defined(SYSTEM_CLK_80MHz)
#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 8 * 1) / 2)
#elif defined(SYSTEM_CLK_60MHz)
#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 6 * 1) / 2)
#endif
//
// 25MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default
// low speed peripheral clock divider of 4. Update the code below if a
// different LSPCLK divider is used!
//
#define DEVICE_LSPCLK_FREQ (DEVICE_SYSCLK_FREQ / 4)
//*****************************************************************************
//
// Macro to call SysCtl_delay() to achieve a delay in microseconds. The macro
// will convert the desired delay in microseconds to the count value expected
// by the function. \b x is the number of microseconds to delay.
//
//*****************************************************************************
#define DEVICE_DELAY_US(x) SysCtl_delay(((((long double)(x)) / (1000000.0L / \
(long double)DEVICE_SYSCLK_FREQ)) - 9.0L) / 5.0L)

//*****************************************************************************
//
// Defines, Globals, and Header Includes related to Flash Support
//
//*****************************************************************************
#ifdef _FLASH
#include <stddef.h>

extern uint16_t RamfuncsLoadStart;
extern uint16_t RamfuncsLoadEnd;
extern uint16_t RamfuncsLoadSize;
extern uint16_t RamfuncsRunStart;
extern uint16_t RamfuncsRunEnd;
extern uint16_t RamfuncsRunSize;

#if defined(SYSTEM_CLK_120MHz)
#define DEVICE_FLASH_WAITSTATES 2
#elif defined(SYSTEM_CLK_100MHz)
#define DEVICE_FLASH_WAITSTATES 2
#elif defined(SYSTEM_CLK_80MHz)
#define DEVICE_FLASH_WAITSTATES 3
#elif defined(SYSTEM_CLK_60MHz)
#define DEVICE_FLASH_WAITSTATES 5
#endif

Is there anybody succeeding in making it work?

Thank you.

over 3 years ago

0 Hareesh Janakiraman over 3 years ago

TI__Guru* 95315 points

There is absolutely no reason why the device would not work at 60 MHz, especially if it works fine at other frequencies. Please check what values are written into the registers.

One thing I noticed (this may not have anything to do with your problem). Your wait-state configuration is incorrect. Even at 120 MHz, only 2 wait-states are needed. Please refer to Table 7-4. Flash Wait States in page 54 of www.ti.com/lit/SPRS902J:

#if defined(SYSTEM_CLK_120MHz)

#define DEVICE_FLASH_WAITSTATES 2

#elif defined(SYSTEM_CLK_100MHz)

#define DEVICE_FLASH_WAITSTATES 2

#elif defined(SYSTEM_CLK_80MHz)

#define DEVICE_FLASH_WAITSTATES 3

#elif defined(SYSTEM_CLK_60MHz)

#define DEVICE_FLASH_WAITSTATES 5

#endif

0 EUN WOO LEE82 over 3 years ago in reply to Hareesh Janakiraman

Intellectual 255 points

I modified the value of DEVICE_FLASH_WAITSTATES as you said.

But the problem persisted.

I connected a JTAG debugger (XDS110 USB Probe) and found where the problem is.

The problem occurs in the function SysCtl_setClock below.

When System Clock is set to 60MHz, the variable 'sysclkInvalidFreq' [line 425] is set to true (1),

So watchdog is serviced and CPU is reset.

What is this clock error ? And Why is this happening?

This is some experimental result.

oscillator clk	20	20	20	20
SystemClk[MHz]	60	80	100	120
mult	6	8	10	12
div	4	4	4	4
ctrl	6149	4120	5146	6158
TMR2INPCLKCTR	2048	2048	2048	2048
mult/div	1.5	2	2.5	3
ctrl/TMR2INPCLK	3.002441406	2.01171875	2.5127	3.00684

Thank you.

bool
SysCtl_setClock(uint32_t config)
{
    uint16_t divSel;
    uint16_t iMult = 0U, fMult = 0U, pllMult = 0U, div;
    bool status, sysclkInvalidFreq = true;
    uint16_t i, tempSCSR, tempWDCR, tempWDWCR, intStatus;
    uint16_t t1TCR, t1TPR, t1TPRH, t2TCR, t2TPR, t2TPRH, t2CLKCTL;
    uint32_t t1PRD, t2PRD, ctr1;
    float32_t sysclkToInClkError, mult;

    //
    // Check the arguments.
    //
    ASSERT((config & SYSCTL_OSCSRC_M) != SYSCTL_OSCSRC_M); // 3 is not valid

    //
    // Don't proceed to the PLL initialization if an MCD failure is detected.
    //
    if(SysCtl_isMCDClockFailureDetected())
    {
        //
        // OSCCLKSRC2 failure detected. Returning false. You'll need to clear
        // the MCD error.
        //
        status = false;
    }
    else
    {
        //
        // Configure oscillator source
        //
        SysCtl_selectOscSource(config & SYSCTL_OSCSRC_M);

        //
        // Bypass PLL
        //
        EALLOW;
        HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &=
            ~SYSCTL_SYSPLLCTL1_PLLCLKEN;
        EDIS;

        //
        // Delay of at least 120 OSCCLK cycles required post PLL bypass
        //
        SysCtl_delay(23U);

        //
        // Configure PLL if enabled
        //
        EALLOW;
        if((config & SYSCTL_PLL_ENABLE) == SYSCTL_PLL_ENABLE)
        {
            if((HWREGH(DEVCFG_BASE + SYSCTL_O_SYSDBGCTL) &
                SYSCTL_SYSDBGCTL_BIT_0) != 0U)
            {
                //
                // The user can optionally insert handler code here. This will
                // only be executed if a watchdog reset occurred after a failed
                // system PLL initialization. See your device user's guide for
                // more information.
                //
                // If the application has a watchdog reset handler, this bit
                // should be checked to determine if the watchdog reset
                // occurred because of the PLL.
                //
                // No action here will continue with retrying the PLL as
                // normal.
                //
            }

            //
            // Set dividers to /1
            //
            HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) = 0U;

            //
            // Get the PLL multiplier settings from config
            //
            iMult |= (uint16_t)(config & SYSCTL_IMULT_M);
            fMult |= (uint16_t)((config & SYSCTL_FMULT_M) >> SYSCTL_FMULT_S);
            pllMult |= (iMult << SYSCTL_SYSPLLMULT_IMULT_S) |
                       (fMult << SYSCTL_SYSPLLMULT_FMULT_S);

            //
            // Lock the PLL five times. This helps ensure a successful start.
            // Five is the minimum recommended number. The user can increase
            // this number according to allotted system initialization time.
            //
            for(i = 0U; i < 5U; i++)
            {
                //
                // Turn off PLL
                //
                HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &=
                    ~SYSCTL_SYSPLLCTL1_PLLEN;

                asm(" RPT #60 || NOP");

                //
                // Write multiplier, which automatically turns on the PLL
                //
                HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) = pllMult;

                //
                // Wait for the SYSPLL lock counter
                //
                while((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLSTS) &
                       SYSCTL_SYSPLLSTS_LOCKS) == 0U)
                {
                    //
                    // Consider to servicing the watchdog using
                    // SysCtl_serviceWatchdog()
                    //
                }
            }
        }

        //
        // Configure Dividers. Set divider to produce slower output frequency
        // to limit current increase.
        //
        divSel = (uint16_t)(config & SYSCTL_SYSDIV_M) >> SYSCTL_SYSDIV_S;

        if(divSel != (126U / 2U))
        {
            HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) =
                (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) &
                ~(uint16_t)SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) | (divSel + 1U);
        }
        else
        {
            HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) =
                (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) &
                 ~(uint16_t)SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) | divSel;
        }

        //
        //      *CAUTION*
        // It is recommended to use the following watchdog code to monitor the
        // PLLstartup sequence. If your application has already cleared the
        // watchdog SCRS[WDOVERRIDE] bit this cannot be done. It is recommended
        // not to clear this bit until after the PLL has been initiated.
        //

        //
        // Backup User Watchdog
        //
        tempSCSR = HWREGH(WD_BASE + SYSCTL_O_SCSR);
        tempWDCR = HWREGH(WD_BASE + SYSCTL_O_WDCR);
        tempWDWCR = HWREGH(WD_BASE + SYSCTL_O_WDWCR);

        //
        // Disable windowed functionality, reset counter
        //
        HWREGH(WD_BASE + SYSCTL_O_WDWCR) = 0x0U;
        SysCtl_serviceWatchdog();

        //
        // Disable global interrupts
        //
        intStatus = __disable_interrupts();

        //
        // Configure for watchdog reset and to run at max frequency
        //
        EALLOW;
        HWREGH(WD_BASE + SYSCTL_O_SCSR) = 0x0U;
        HWREGH(WD_BASE + SYSCTL_O_WDCR) = SYSCTL_WD_CHKBITS;

        //
        // This bit is reset only by power-on-reset (POR) and will not be
        // cleared by a WD reset
        //
        HWREGH(DEVCFG_BASE + SYSCTL_O_SYSDBGCTL) |= SYSCTL_SYSDBGCTL_BIT_0;

        //
        // Enable PLLSYSCLK is fed from system PLL clock
        //
        HWREGH(CLKCFG_BASE +
               SYSCTL_O_SYSPLLCTL1) |= SYSCTL_SYSPLLCTL1_PLLCLKEN;

        EDIS;

        //
        // Delay to ensure system is clocking from PLL prior to clearing
        // status bit
        //
        SysCtl_delay(3U);

        //
        // Slip Bit Monitor and SYSCLK Frequency Check using timers
        // Re-lock routine for SLIP condition or if SYSCLK and CLKSRC timer
        // counts are off by +/- 10%. At a minimum, SYSCLK check is performed.
        // Re-lock attempt is carried out if SLIPS bit is set.
        // This while loop is monitored by watchdog.
        // In the event that the PLL does not successfully lock, the loop will
        // be aborted by watchdog reset.
        //
        while(((config & SYSCTL_PLL_ENABLE) == SYSCTL_PLL_ENABLE) &&
              (sysclkInvalidFreq == true))
        {
            EALLOW;

            //
            // Perform PLL re-lock only if SLIPS bit is set, otherwise monitor
            // SYSCLK frequency with timers
            //
            if((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLSTS) &
                SYSCTL_SYSPLLSTS_SLIPS) == 1U)
            {
                //
                // Bypass PLL
                //
                HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &=
                    ~SYSCTL_SYSPLLCTL1_PLLCLKEN;

                //
                // Delay of at least 120 OSCCLK cycles required post PLL bypass
                //
                SysCtl_delay(23U);

                //
                // Turn off PLL
                //
                HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &=
                    ~SYSCTL_SYSPLLCTL1_PLLEN;

                SysCtl_delay(3U);

                //
                // Write multiplier, which automatically turns on the PLL
                //
                HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) |= pllMult;

                //
                // Wait for the SYSPLL lock counter
                //
                while((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLSTS) &
                        SYSCTL_SYSPLLSTS_LOCKS) == 0U)
                {
                    ;
                }

                //
                // Enable PLLSYSCLK is fed from system PLL clock
                //
                HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) |=
                    SYSCTL_SYSPLLCTL1_PLLCLKEN;

                //
                // Delay to ensure system is clocking from PLL prior to
                // clearing status bit
                //
                SysCtl_delay(3U);
            }

            //
            // Backup timer1 and timer2 settings
            //
            t1TCR = HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR);
            t1PRD = HWREG(CPUTIMER1_BASE + CPUTIMER_O_PRD);
            t1TPR = HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPR);
            t1TPRH = HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPRH);
            t2CLKCTL = HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL);
            t2TCR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR);
            t2PRD = HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD);
            t2TPR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR);
            t2TPRH = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH);

            //
            // Set up timers 1 and 2
            // Configure timer1 to count SYSCLK cycles
            //

            //
            // Stop timer 1
            // Seed timer1 counter
            // Set sysclock divider
            // Reload timer with value in PRD
            // Clear interrupt flag
            // Enable interrupt
            //
            HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS;
            HWREG(CPUTIMER1_BASE + CPUTIMER_O_PRD) = (uint32_t)TMR1SYSCLKCTR;
            HWREG(CPUTIMER1_BASE + CPUTIMER_O_TPR) = 0U;
            HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB;
            HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF;
            HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIE;

            //
            // Configure timer2 to count Input clock cycles
            //
            switch (config & SYSCTL_OSCSRC_M)
            {
                case SYSCTL_OSCSRC_OSC1:
                    //
                    // Clk Src = INT_OSC1
                    //
                    HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) &=
                        ~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M;
                    HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) |= 1U;
                    break;

                case SYSCTL_OSCSRC_OSC2:
                    //
                    // Clk Src = INT_OSC2
                    //
                    HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) &=
                        ~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M;
                    HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) |= 2U;
                    break;

                case SYSCTL_OSCSRC_XTAL:
                    //
                    // Clk Src = XTAL
                    //
                    HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) &=
                        ~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M;
                    HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) |= 3U;
                    break;

                default:
                    //
                    // Do nothing. Not a valid clock source value.
                    //
                    break;
            }

            //
            // Clear interrupt flag
            // Enable interrupt
            // Stop timer 2
            // Seed timer2 counter
            // Set sysclock divider
            // Reload timer with value in PRD
            //
            HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF;
            HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIE;
            HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS;
            HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = (uint32_t)TMR2INPCLKCTR;
            HWREG(CPUTIMER2_BASE + CPUTIMER_O_TPR) = 0U;
            HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB;

            //
            // Stop/Start timer counters
            //

            //
            // Stop timer 1
            // Stop timer 2
            // Reload timer1 with value in PRD
            // Reload timer2 with value in PRD
            // Clear timer2 interrupt flag
            // Start timer2
            // Start timer1
            //
            HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS;
            HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS;
            HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB;
            HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB;
            HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF;
            HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS;
            HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS;

            //
            // Wait for Timers - Stop if either timer overflows
            //
            while(((HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) &
                   CPUTIMER_TCR_TIF) == 0U)  &&
                  ((HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) &
                   CPUTIMER_TCR_TIF) == 0U))
            {
                ;
            }

            //
            // Stop timer 1 and 2
            //
            HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS;
            HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS;

            //
            // Calculate elapsed counts on timer1
            //
            ctr1 = (uint32_t)TMR1SYSCLKCTR - HWREG(CPUTIMER1_BASE +
                                                   CPUTIMER_O_TIM);

            //
            // Restore timer settings
            //
            HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) = t1TCR;
            HWREG(CPUTIMER1_BASE + CPUTIMER_O_PRD) = t1PRD;
            HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPR) = t1TPR;
            HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPRH) = t1TPRH;
            HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = t2CLKCTL;
            HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) = t2TCR;
            HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = t2PRD;
            HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR) = t2TPR;
            HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH) = t2TPRH;

            //
            // Calculate Clock Error:
            // Error = (mult/div) - (timer1 count/timer2 count)
            //
            mult = (float32_t)iMult + ((float32_t)fMult / 4.0F);

            if((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & 0x3FU) == 0U)
            {
                div = 1U;
            }
            else
            {
                div = (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) &
                       0x3FU) << 1;
            }

            sysclkToInClkError = (mult / (float32_t)div) -
                                 ((float32_t)ctr1 / (float32_t)TMR2INPCLKCTR);

            //
            // sysclkInvalidFreq will be set to true if sysclkToInClkError is
            // off by 10%
            //
            sysclkInvalidFreq = ((sysclkToInClkError > 0.10F) ||
                                 (sysclkToInClkError < -0.10F));

            EDIS;
        }

        //
        // Clear bit
        //
        EALLOW;
        HWREGH(DEVCFG_BASE + SYSCTL_O_SYSDBGCTL) &= ~SYSCTL_SYSDBGCTL_BIT_0;
        EDIS;

        //
        // Restore user watchdog, first resetting counter
        //
        SysCtl_serviceWatchdog();

        //
        // Set the KEY bits and make sure not to set the WDOVERRIDE bit
        //
        EALLOW;
        HWREGH(WD_BASE + SYSCTL_O_WDCR) = tempWDCR | SYSCTL_WD_CHKBITS;
        HWREGH(WD_BASE + SYSCTL_O_WDWCR) = tempWDWCR;
        HWREGH(WD_BASE + SYSCTL_O_SCSR) = tempSCSR & ~SYSCTL_SCSR_WDOVERRIDE;
        EDIS;

        //
        // Restore state of ST1[INTM]. This was set by the
        // __disable_interrupts() intrinsic previously.
        //
        if((intStatus & 0x1U) == 0U)
        {
            EINT;
        }

        //
        // Restore state of ST1[DBGM]. This was set by the
        // __disable_interrupts() intrinsic previously.
        //
        if((intStatus & 0x2U) == 0U)
        {
            SYSCTL_CLRC_DBGM;
        }

        //
        // ~200 PLLSYSCLK delay to allow voltage regulator to stabilize prior
        // to increasing entire system clock frequency.
        //
        SysCtl_delay(40U);

        //
        // Set the divider to user value
        //
        EALLOW;
        HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) =
            (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) &
             ~SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) | divSel;
        EDIS;

        status = true;
    }

    return(status);
}

0 Hareesh Janakiraman over 3 years ago in reply to EUN WOO LEE82

TI__Guru* 95315 points

This may need to be addressed by someone in the software team. What version of C2000ware are you using? If you are not using the latest version (4.01), please download and install it.

0 EUN WOO LEE82 over 3 years ago in reply to Hareesh Janakiraman

Intellectual 255 points

C2000Ware version I'm using is 4.01 from the beginning.

When the clock setting is 60MHz, sysclkToInClkError is out of allowed range. I tested for the various frequency.

The test passed up to 72MHz and failed at 60MHz and 70MHz.

I also tested both 28075 100pin and 176pin. The result was the same.

            sysclkToInClkError = (mult / (float32_t)div) -
                                 ((float32_t)ctr1 / (float32_t)TMR2INPCLKCTR);

            //
            // sysclkInvalidFreq will be set to true if sysclkToInClkError is
            // off by 10%
            //
            sysclkInvalidFreq = ((sysclkToInClkError > 0.10F) ||
                                 (sysclkToInClkError < -0.10F));

+1 Veena Kamath over 3 years ago in reply to EUN WOO LEE82

TI__Mastermind 32655 points

Hi,

EUN WOO LEE82 said:
div 4 4 4 4

I believe you meant div=2 for all scenarios

As per the spec, the PLLRAWCK should be between 120-400

In your case, PLLRAWCLK is 20*6 = 120. Can you try with a different multiplier and divider (Eg: 20 * 12 /4) to ensure the internal frequencies are not at the border of the allowed range?

Regards,

Veena

0 EUN WOO LEE82 over 3 years ago in reply to Veena Kamath

Intellectual 255 points

'div' in the table is not register setting, but variable in the code as below.

div = (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) &
0x3FU) << 1;

And the value of div came out as 4.

I changed the code in device.h like this.

[ASIS]

#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(6) | \
SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \
SYSCTL_PLL_ENABLE)

[TOBE]

#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(12) | \
SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(4) | \
SYSCTL_PLL_ENABLE)

After that, the error disappeared.

Thank you.

C2000™︎ microcontrollers

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