TMS320F280049: CMPSS issue

Even use CMPSS_disableModule(), the trip would be still triggered. Here are the configuration codes of CMPSS.

void InitCMPSS(void)
{
InitCMPSS1();
InitCMPSS2();
InitCMPSS3();
InitCMPSS4();
InitCMPSS5();
InitCMPSS6();

EALLOW;

//ePWM XBAR Mux Configuration for TRIP4
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX0 = 0;
//ePWM XBAR Mux Enable for TRIP4
EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX0 = 1;

//ePWM XBAR Mux Configuration for TRIP4
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX2 = 1;
//ePWM XBAR Mux Enable for TRIP4
EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX2 = 1;

//ePWM XBAR Mux Configuration for TRIP4
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX4 = 0;
//ePWM XBAR Mux Enable for TRIP4
EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX4 = 1;

//ePWM XBAR Mux Configuration for TRIP4
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX6 = 0;
//ePWM XBAR Mux Enable for TRIP4
EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX6 = 1;

//ePWM XBAR Mux Configuration for TRIP4
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX8 = 0;
//ePWM XBAR Mux Enable for TRIP4
EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX8 = 1;

XbarRegs.XBARCLR1.all = 0xFFFFFFFF;
EPwm1Regs.TZCLR.all = 0xFFFF;
EPwm2Regs.TZCLR.all = 0xFFFF;
EPwm3Regs.TZCLR.all = 0xFFFF;
EPwm5Regs.TZCLR.all = 0xFFFF;
EPwm6Regs.TZCLR.all = 0xFFFF;
EPwm1Regs.TZOSTCLR.all = 0xFFFF;
EPwm2Regs.TZOSTCLR.all = 0xFFFF;
EPwm3Regs.TZOSTCLR.all = 0xFFFF;
EPwm5Regs.TZOSTCLR.all = 0xFFFF;
EPwm6Regs.TZOSTCLR.all = 0xFFFF;

EDIS;
}

void InitCMPSS1(void)
{
EALLOW;
//CMPSS input mux select.
AnalogSubsysRegs.CMPHPMXSEL.bit.CMP1HPMXSEL = CMPSS_CH_PV2_CURR;

//High comparator input source.
//0 Internal DAC
//1 External pin
Cmpss1Regs.COMPCTL.bit.COMPHSOURCE = 0;
//Comparator/DAC enable.
Cmpss1Regs.COMPCTL.bit.COMPDACE = 1;
//DAC reference select.
//0 VDDA
//1 VDAC
Cmpss1Regs.COMPDACCTL.bit.SELREF = 1;
//High DAC shadow value.
Cmpss1Regs.DACHVALS.bit.DACVAL = CMPSS_DACH_PV2_CURR;

//Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1.
Cmpss1Regs.CTRIPHFILCLKCTL.bit.CLKPRESCALE = 1;
//Low filter sample window size. Number of samples to monitor is SAMPWIN+1.
Cmpss1Regs.CTRIPHFILCTL.bit.SAMPWIN = FILTER_WINDOW - 1;
//Low filter majority voting threshold.Threshold used is THRESH+1.THRESH should be GREATER than half of SAMPWIN
Cmpss1Regs.CTRIPHFILCTL.bit.THRESH = FILTER_THRESHOLD - 1;
//Low filter initialization.
Cmpss1Regs.CTRIPHFILCTL.bit.FILINIT = 1;
//High comparator CTRIPH source select.
//0 Asynchronous comparator output drives CTRIPH
//1 Synchronous comparator output drives CTRIPH
//2 Output of digital filter drives CTRIPH
//3 Latched output of digital filter drives CTRIPH
Cmpss1Regs.COMPCTL.bit.CTRIPHSEL = 2;

EDIS;
}

void InitCMPSS2(void)
{
EALLOW;
//CMPSS input mux select.
AnalogSubsysRegs.CMPHPMXSEL.bit.CMP2HPMXSEL = CMPSS_CH_INV_CURR;
AnalogSubsysRegs.CMPLPMXSEL.bit.CMP2LPMXSEL = CMPSS_CH_INV_CURR;

//High comparator input source.
//0 Internal DAC
//1 External pin
Cmpss2Regs.COMPCTL.bit.COMPHSOURCE = 0;
Cmpss2Regs.COMPCTL.bit.COMPLSOURCE = 0;
//Comparator/DAC enable.
Cmpss2Regs.COMPCTL.bit.COMPDACE = 1;
//DAC reference select.
//0 VDDA
//1 VDAC
Cmpss2Regs.COMPDACCTL.bit.SELREF = 1;
//High DAC shadow value.
Cmpss2Regs.DACHVALS.bit.DACVAL = CMPSS_DACH_INV_CURR;
Cmpss2Regs.DACLVALS.bit.DACVAL = CMPSS_DACL_INV_CURR;

//Cmpss2Regs.COMPHYSCTL.bit.COMPHYS = 2;

//Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1.
Cmpss2Regs.CTRIPHFILCLKCTL.bit.CLKPRESCALE = 1;
Cmpss2Regs.CTRIPLFILCLKCTL.bit.CLKPRESCALE = 1;
//Low filter sample window size. Number of samples to monitor is SAMPWIN+1.
Cmpss2Regs.CTRIPHFILCTL.bit.SAMPWIN = FILTER_WINDOW - 1;
Cmpss2Regs.CTRIPLFILCTL.bit.SAMPWIN = FILTER_WINDOW - 1;
//Low filter majority voting threshold.Threshold used is THRESH+1.THRESH should be GREATER than half of SAMPWIN
Cmpss2Regs.CTRIPHFILCTL.bit.THRESH = FILTER_THRESHOLD - 1;
Cmpss2Regs.CTRIPLFILCTL.bit.THRESH = FILTER_THRESHOLD - 1;
//Low filter initialization.
Cmpss2Regs.CTRIPHFILCTL.bit.FILINIT = 1;
Cmpss2Regs.CTRIPLFILCTL.bit.FILINIT = 1;

//Comparator output invert.
Cmpss2Regs.COMPCTL.bit.COMPHINV = 0;
Cmpss2Regs.COMPCTL.bit.COMPLINV = 1;
//High comparator CTRIPH source select.
//0 Asynchronous comparator output drives CTRIPH
//1 Synchronous comparator output drives CTRIPH
//2 Output of digital filter drives CTRIPH
//3 Latched output of digital filter drives CTRIPH
Cmpss2Regs.COMPCTL.bit.CTRIPHSEL = 2;
Cmpss2Regs.COMPCTL.bit.CTRIPLSEL = 2;

EDIS;
}
void InitCMPSS3(void)
{
EALLOW;
// CMPSS input mux select.
AnalogSubsysRegs.CMPHPMXSEL.bit.CMP3HPMXSEL = CMPSS_CH_PV1_CURR;

//High comparator input source.
//0 Internal DAC
//1 External pin
Cmpss3Regs.COMPCTL.bit.COMPHSOURCE = 0;
//Comparator/DAC enable.
Cmpss3Regs.COMPCTL.bit.COMPDACE = 1;
//DAC reference select.
//0 VDDA
//1 VDAC
Cmpss3Regs.COMPDACCTL.bit.SELREF = 1;
//High DAC shadow value.
Cmpss3Regs.DACHVALS.bit.DACVAL = CMPSS_DACH_PV1_CURR;

//Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1.
Cmpss3Regs.CTRIPHFILCLKCTL.bit.CLKPRESCALE = 1;
//Low filter sample window size. Number of samples to monitor is SAMPWIN+1.
Cmpss3Regs.CTRIPHFILCTL.bit.SAMPWIN = FILTER_WINDOW - 1;
//Low filter majority voting threshold.Threshold used is THRESH+1.THRESH should be GREATER than half of SAMPWIN
Cmpss3Regs.CTRIPHFILCTL.bit.THRESH = FILTER_THRESHOLD - 1;
//Low filter initialization.
Cmpss3Regs.CTRIPHFILCTL.bit.FILINIT = 1;
//High comparator CTRIPH source select.
//0 Asynchronous comparator output drives CTRIPH
//1 Synchronous comparator output drives CTRIPH
//2 Output of digital filter drives CTRIPH
//3 Latched output of digital filter drives CTRIPH
Cmpss3Regs.COMPCTL.bit.CTRIPHSEL = 2;

EDIS;
}

void InitCMPSS4(void)
{
EALLOW;
// CMPSS input mux select.
AnalogSubsysRegs.CMPHPMXSEL.bit.CMP4HPMXSEL = CMPSS_CH_PV3_CURR;

//High comparator input source.
//0 Internal DAC
//1 External pin
Cmpss4Regs.COMPCTL.bit.COMPHSOURCE = 0;
//Comparator/DAC enable.
Cmpss4Regs.COMPCTL.bit.COMPDACE = 1;
//DAC reference select.
//0 VDDA
//1 VDAC
Cmpss4Regs.COMPDACCTL.bit.SELREF = 1;
//High DAC shadow value.
Cmpss4Regs.DACHVALS.bit.DACVAL = CMPSS_DACH_PV3_CURR;

//Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1.
Cmpss4Regs.CTRIPHFILCLKCTL.bit.CLKPRESCALE = 1;
//Low filter sample window size. Number of samples to monitor is SAMPWIN+1.
Cmpss4Regs.CTRIPHFILCTL.bit.SAMPWIN = FILTER_WINDOW - 1;
//Low filter majority voting threshold.Threshold used is THRESH+1.THRESH should be GREATER than half of SAMPWIN
Cmpss4Regs.CTRIPHFILCTL.bit.THRESH = FILTER_THRESHOLD - 1;
//Low filter initialization.
Cmpss4Regs.CTRIPHFILCTL.bit.FILINIT = 1;
//High comparator CTRIPH source select.
//0 Asynchronous comparator output drives CTRIPH
//1 Synchronous comparator output drives CTRIPH
//2 Output of digital filter drives CTRIPH
//3 Latched output of digital filter drives CTRIPH
Cmpss4Regs.COMPCTL.bit.CTRIPHSEL = 2;

EDIS;
}

void InitCMPSS5(void)
{
EALLOW;
// CMPSS input mux select.
AnalogSubsysRegs.CMPHPMXSEL.bit.CMP5HPMXSEL = CMPSS_CH_BUS_VOLT;

//High comparator input source.
//0 Internal DAC
//1 External pin
Cmpss5Regs.COMPCTL.bit.COMPHSOURCE = 0;
//Comparator/DAC enable.
Cmpss5Regs.COMPCTL.bit.COMPDACE = 1;
//DAC reference select.
//0 VDDA
//1 VDAC
Cmpss5Regs.COMPDACCTL.bit.SELREF = 1;
//High DAC shadow value.
Cmpss5Regs.DACHVALS.bit.DACVAL = CMPSS_DACH_BUS_VOLT;

//Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1.
Cmpss5Regs.CTRIPHFILCLKCTL.bit.CLKPRESCALE = 1;
//Low filter sample window size. Number of samples to monitor is SAMPWIN+1.
Cmpss5Regs.CTRIPHFILCTL.bit.SAMPWIN = FILTER_WINDOW - 1;
//Low filter majority voting threshold.Threshold used is THRESH+1.THRESH should be GREATER than half of SAMPWIN
Cmpss5Regs.CTRIPHFILCTL.bit.THRESH = FILTER_THRESHOLD - 1;
//Low filter initialization.
Cmpss5Regs.CTRIPHFILCTL.bit.FILINIT = 1;
//High comparator CTRIPH source select.
//0 Asynchronous comparator output drives CTRIPH
//1 Synchronous comparator output drives CTRIPH
//2 Output of digital filter drives CTRIPH
//3 Latched output of digital filter drives CTRIPH
Cmpss5Regs.COMPCTL.bit.CTRIPHSEL = 2;

EDIS;
}
void InitCMPSS6(void)
{
EALLOW;
// CMPSS input mux select.
AnalogSubsysRegs.CMPHPMXSEL.bit.CMP6HPMXSEL = CMPSS_CH_GRID_VOLT;

//High comparator input source.
//0 Internal DAC
//1 External pin
Cmpss6Regs.COMPCTL.bit.COMPHSOURCE = 0;
//Comparator/DAC enable.
Cmpss6Regs.COMPCTL.bit.COMPDACE = 1;
//DAC reference select.
//0 VDDA
//1 VDAC
Cmpss6Regs.COMPDACCTL.bit.SELREF = 1;
//High DAC shadow value.
Cmpss6Regs.DACHVALS.bit.DACVAL = CMPSS_DACH_GRID_VOLT;

//Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1.
Cmpss6Regs.CTRIPHFILCLKCTL.bit.CLKPRESCALE = CMPSS_CLK_GRID_VOLT-1;
//Low filter sample window size. Number of samples to monitor is SAMPWIN+1.
Cmpss6Regs.CTRIPHFILCTL.bit.SAMPWIN = FILTER_WINDOW - 1;
//Low filter majority voting threshold.Threshold used is THRESH+1.THRESH should be GREATER than half of SAMPWIN
Cmpss6Regs.CTRIPHFILCTL.bit.THRESH = FILTER_THRESHOLD - 1;
//Low filter initialization.
Cmpss6Regs.CTRIPHFILCTL.bit.FILINIT = 1;
//High comparator CTRIPH source select.
//0 Asynchronous comparator output drives CTRIPH
//1 Synchronous comparator output drives CTRIPH
//2 Output of digital filter drives CTRIPH
//3 Latched output of digital filter drives CTRIPH
Cmpss6Regs.COMPCTL.bit.CTRIPHSEL = 2;
//Cmpss6Regs.COMPCTL.bit.CTRIPOUTHSEL = 2;

EDIS;
}

Angela,

Going to your original post, even if the clock is disabled to the CMPSS if it is setup already it will continue to function with whatever static values were there before the clock was removed.  So I think that behavior will be expected.

Now, if we disable the CMPSS with the COMPDACE bit(s) this is something I need to understand a bit more. 

For the XBARFLG1 register is customer seeing this get set again, even after clearing the flags after the COMPDACE bit(s) are set to 0? 

Could customer try and change the COMPTCTL[CTRIPOUTHSEL/CTRIPOUTLSEL] to see if that will remove the output to the XBAR, i.e. if they are using SYNC/LATCH/COMPSTS, change to ASYNC to see if that clears the condition?  The theory here is that the digital logic is still retaining the old comparator output even though it is disabled.

Let me know if you think I am understanding the issue correctly as well.

Best,

Matthew

Hi Matthew,

Even after clearing the flags after the COMPDACE bit(s) are set to 0, the XBARFLG1 register will get set again.

Hi Matthew,

I saw someone said that the reference of ADC and DAC will effect the XBARFLG. Is that right? Another question is will it be useful to change the Hysteresis width? Can you see anything unusual from their configuration?

Could customer try and change the COMPTCTL[CTRIPOUTHSEL/CTRIPOUTLSEL] to see if that will remove the output to the XBAR, i.e. if they are using SYNC/LATCH/COMPSTS, change to ASYNC to see if that clears the condition?

They tried this, there was no change. They have tried these before and had not improved:

1. Change the DAC reference source
2. Change whether the digital filtered output is selected
3. Modify the COMPTTL[CTRIPOUTHSEL/CTRIPOUTLSEL] to ASYNC
4. Increased CTRIPHFILCTL.bit.SAMPWIN value andCTRIPHFILCTL.bit.test value
5. Turn off the module clock of the unused comparator.The comparator configuration is also not initialized

Behavior: Unused comparators can trip.The comparator used can also trip if the set value is not reached;
They only use high side comparators for current detection, but low side also triggers.

Angela,

The ADC/DAC have a reference select that will impact their use, but if we disable the comparator we should not see those values propagate.  I need to loop in some other folks to this discussion, it may need another day before I have an answer.

Best,

Matthew

Angela,

I cannot replicate the issue on the LAUNCHXL-F280049 I have in the office.  When I clear the COMPDACE bit I see the local COMPSTS bits go to 0 immediately and the latch bits retain their value.  With COMPDACE cleared if I look at the XBARFLAGs corresponding to these signals if I clear them out they do not get set again, until I set the COMPDACE bit again to a 1.

So with COMPDACE = 0 I don't see any signals propagate from the CMPSS to the XBARFLAG register.  Is there another signal I should examine to see if the COMPDACE bit has a different effect?

Best,

Matthew

Hi Matthew,

Is it possible that there is somewhere broken in the chip?

Hi Matthew,

I got the information that they replaced the chip with a good one, the issue still existed. They suspect that there is something wrong with their design. Could you help review the hardware and software?

Angela,

We can request a review be done internally.  Can you start an email conversation off forum so we can share the schematics/SW privately?

Best,

Matthew

Hi Matthew,

Could you share the demo you used to replicate the issue on the LAUNCHXL-F280049. My customer will send me the SW/HW later, and I will send them to you through email. Thanks a lot for your help.

Angela,

I just used one of the C2000Ware examples, and sysconfig to configure the CMPSS and the BUFDAC(would need to jumper wire DACOUT to CMPSSIN) to get the CMPSS to have a trip event.  I then added the XBARFLAG to the watchwindow in CCS and observed the behavior when I set/cleared COMPDACE bit.

Customer could also bring out the CMPSTS onto a GPIO using the OUTPUT XBAR.

Best,

Matthew