TMS320F280049C: TIDM-02002 : IPRIM_TANK / ISEC_TANK ADC Samples

Hello,

In TIDM-02002, it seems that IPRIM_TANK/ISEC_TANK are not measured by ADC, they are just used as CMPSS trip inputs. However it appears some code already exists to implement ADC readings but it appears incomplete/inconsistent. I'd like to understand the designer's intention assuming ADC readings are implemented because our design does require ADC readings for IPRIM_TANK and SEC_TANK so I'm trying to activate and augment the existing code.

Q1:

C:\ti\c2000\C2000Ware_DigitalPower_SDK_4_01_00_00\solutions\tidm_02002\f28004x\drivers\source\clllc_hal.c, lines 1170 to 1187:

    //
    // for the faster signals such as shunt current sense, the PWM time base of
    // the module used to control the power stage must be used.
    // Also as we are interested in the peak value we must sample close to the
    // falling edge of the leg1 H PWM
    // Select SOC from counter at ctr =CMPA
    //
    EPWM_setADCTriggerSource(CLLLC_PRIM_LEG1_PWM_BASE,
                             EPWM_SOC_A, EPWM_SOC_TBCTR_U_CMPD);
    //
    // CMPA is updated in the ISR so nothing to do here
    // pre-scale the trigger of the ADC conversion
    //
    EPWM_setADCTriggerEventPrescale(CLLLC_PRIM_LEG1_PWM_BASE,
                                        EPWM_SOC_A, 6);

    EPWM_enableADCTrigger(CLLLC_PRIM_LEG1_PWM_BASE,
                          EPWM_SOC_A);

Lines 1173 and 1174 say that "we are interested in the peak value we must sample close to the falling edge of the leg1 H PWM Select SOC from counter at ctr =CMPA".

Assuming that is the case, shouldn't the 3rd argument to EPWM_setADCTriggerSource() refer to i) CMPA and ii) when CTR is counting down? In other words shouldn't it be:

    EPWM_setADCTriggerSource(CLLLC_PRIM_LEG1_PWM_BASE,
                             EPWM_SOC_A, EPWM_SOC_TBCTR_D_CMPA);

Q2:

Lines 1287 and 1288 generate an SOC on every 6th event:

    EPWM_setADCTriggerEventPrescale(CLLLC_PRIM_LEG1_PWM_BASE,
                                        EPWM_SOC_A, 6);

Why is the SOCA triggered once every six PWM cycles? Where does 6 come from please?

Q3:

C:\ti\c2000\C2000Ware_DigitalPower_SDK_4_01_00_00\solutions\tidm_02002\f28004x\clllc\clllc_user_settings.h, line 200:

#define CLLLC_IPRIM_TANK_ADC_TRIG_SOURCE CLLLC_ADC_TRIG_FAST_SOURCE

CLLLC_ADC_TRIG_FAST_SOURCE is undefined. If it was defined, I assume it would be ADC_TRIGGER_EPWM1_SOCA, is that correct?

Thank you.