TMS320F28379D: Using the same ADCxINTx for different EOC

Hi Erik,

I have assigned this question to our ADC expert, please expect a reply in the near future

Regards,

Peter

Hello Erik,

Looking through the documentation, it does not seem like there is a way to do this using multiple EOCs to trigger an interrupt. What could work instead is you use multiple SOCs to trigger an ADCA INT1 and then using the ADC SOC flag register (ADCSOCFLG1), you can determine which SOC triggered the interrupt and wait for its data [EDIT: This will cause an interrupt overflow, as it will be constantly triggering the interrupt. The better solution is to use one SOC to trigger the interrupt while the other ones still start converting to get their results.]. The wait should not be a significant impact unless you intend to wait for many SOCs at a time. Unfortunately, I cannot see a way of replicating this with an EOC flag of some sort, since there is no way of monitoring EOC status without just a separate interrupt.

Best regards,

Omer Amir

Thank you Omer

I think something like the solution you proposed could work. However, my understanding is that the ADCSOCFLG1 register will have the bits set by the SOC and will be cleared as soon as the SOC is serviced by the ADC. I am needing to read some flag register once ADC conversion is complete and the ADC INTx ISR is entered. Is there a register bit somewhere that would still be set that would correspond to which SOC initiated the latest ADC conversion that triggered this interrupt?

I want the SOC to be automatically triggered by the PWM period counter compare. So I don't want to have to wait after each ADC trigger for the ADC to be complete. This should all be in hardware and then once the ADC is complete, I want to read only the corresponding result of the SOC that initiated that ADC sample. 

Thank you

Erik 

Hello Erik,

To clarify:

Erik Johnson said:

However, my understanding is that the ADCSOCFLG1 register will have the bits set by the SOC and will be cleared as soon as the SOC is serviced by the ADC.

The SOC flag bits are not cleared upon entering the ADC interrupt, they must be cleared manually within the interrupt. Using the ADCINTSOCSEL1/2 registers to configure the ADC SOC interrupts and the ADCSOCFLG1 register to read which SOC has been triggered, you should be able to have multiple SOCs for conversions and then choose which ones service the interrupt. From within the interrupt, you should then be able to see which SOC flags have been raised. The SOCs use a round robin to service the conversions, so there is no inherent priority that will cause one SOC to go to the interrupt over another, besides just being triggered first.

Best regards,

Omer Amir

Thank you Omer

I am not seeing that the SOC flag bits needing to be cleared in the interrupt. My understanding is that the flag bits that need to be cleared in an interrupt are the 1) Clear the interrupt flag, i.e. ADCINTx,  and clear the interrupt group flag, e.g. Group 1. 

• I have put breakpoints at the beginning of my ISR and I do not see that any of the SOC flag bits in the ADCSOCFLG1 register are set.
• The ADCINTSOCSEL1/2 register appears to be for starting a new SOC after the completion of a previous ADC reading by configuring which of any of the ADCINT triggers a selected SOC. 
• The ADCINTSEL1N2 register is for selecting which EOC can trigger an ADC interrupt. It appears that only a single EOC can trigger a selected ADCINTx. (see the register description) Therefore I do not see that it is possible to have multiple EOC trigger the same interrupt. See page 1569 of the technical reference manual. 

Thank you

Erik 

Thank you Omer

The two possible solutions we came to seems to be similar to this. 

Option 1: Cyclically update EOC mapping in ADCINTSEL1N2 within the ISR so that the next SOC triggers the interrupt. Keep a record/queue of which ADC measurement comes next and use this to also decide which update function to run. 

Option 2: Include a common sample to every measurement and have this common sample trigger the interrupt. Keep a record/queue of which distinct sample in addition to the common one to read within the ISR and execute its associated update function.  

Thanks!

Erik 

Hello Erik,

Yes, these options are valid. Let me know if you have any further questions, otherwise I can close this thread.

Best regards,

Omer Amir