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TMS320F280039C: Watchdog Reset after Live Firmware Update

Fernando Gatto
Intellectual 360 points

Part Number: TMS320F280039C
Other Parts Discussed in Thread: TIDM-02011, C2000WARE

Hi Experts:

                 I have modified the Live Firmware Update examples in order to work using CAN interface.

The Kernel receives and flashes the program without any problem. When It finishes, the watchdog is activated

but instead of starting the newly loaded program as it is expected, it jumps to nowhere and gets Frozen.

If I turn off and on the device, then it starts running the new program OK.

I don't know how to find where it could be the problem.

Thanks in advance and regards,

Fernando

  • 0
    TI__Mastermind 24811 points

    Hi Fernando,

    Thank you for reaching out on E2E. I have assigned this question to our expert, you should hear from them shortly

    Regards,

    Peter

  • 0
    TI__Genius 15080 points

    Hi Fernando,

    Have you checked that the starting address for your program is correct in Bank1? Also, if you could provide what your Watchdog Initialization code looks like that would help to understand the problem more. 

    Regards,

    Charles

  • 0 in reply to Charles Roberson
    Intellectual 360 points

    Hi Charles,

    This is the code of the WatchDog Initialization

        //
    // Set the watchdog to generate a reset signal instead of an
    // interrupt signal
    //
    SysCtl_setWatchdogMode(SYSCTL_WD_MODE_RESET);

    //
    // Enable the watchdog
    //
    SysCtl_enableWatchdog();

    //Wait the Timeout
    while(1)
    {

    };

    And this is the Linker config of the Program I am Loading into the Bank1

    MEMORY
{
   BEGIN           	: origin = 0x09EFF0,   length = 0x000002
   BOOT_RSVD        : origin = 0x00000002, length = 0x00000126

   RAMM0            : origin = 0x00000128, length = 0x000002D8
   RAMM1            : origin = 0x00000400, length = 0x000003F8
   // RAMM1_RSVD       : origin = 0x000007F8, length = 0x00000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RAMLS0_LS1_LS2   : origin = 0x00008000, length = 0x00001800
   RAMLS3           : origin = 0x00009800, length = 0x00000800
   RAMLS4           : origin = 0x0000A000, length = 0x00000800
   RAMLS5           : origin = 0x0000A800, length = 0x00000800
   RAMLS6           : origin = 0x0000B000, length = 0x00000800
   RAMLS7           : origin = 0x0000B800, length = 0x00000800

   RAMGS0           : origin = 0x0000C000, length = 0x00001000
   RAMGS1           : origin = 0x0000D000, length = 0x00001000
   RAMGS2           : origin = 0x0000E000, length = 0x00001000
   RAMGS3           : origin = 0x0000F000, length = 0x00000FF8
   // RAMGS3_RSVD      : origin = 0x0000FFF8, length = 0x00000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   BOOTROM          : origin = 0x003F8000, length = 0x00007FC0
   SECURE_ROM       : origin = 0x003F2000, length = 0x00006000

   RESET            : origin = 0x003FFFC0, length = 0x00000002

   /* Flash sectors */


   /* BANK 0 */
   FLASH_BANK0_SEC0  : origin = 0x080002, length = 0x000FFE
   FLASH_BANK0_SEC1  : origin = 0x081000, length = 0x001000
   FLASH_BANK0_SEC2  : origin = 0x082008, length = 0x000FF8
   FLASH_BANK0_SEC3  : origin = 0x083000, length = 0x001000
   FLASH_BANK0_SEC4  : origin = 0x084000, length = 0x001000
   FLASH_BANK0_SEC5  : origin = 0x085000, length = 0x001000
   FLASH_BANK0_SEC6  : origin = 0x086000, length = 0x001000
   FLASH_BANK0_SEC7  : origin = 0x087000, length = 0x001000
   FLASH_BANK0_SEC8  : origin = 0x088000, length = 0x001000
   FLASH_BANK0_SEC9  : origin = 0x089000, length = 0x001000
   FLASH_BANK0_SEC10_11    : origin = 0x08A000, length = 0x002000
   FLASH_BANK0_SEC12_13_14 : origin = 0x08C000, length = 0x002FF0
   FLASH_BANK0_SEC15 : origin = 0x08EFF2, length = 0x000FFE


   /* BANK 1 */
   FLASH_BANK1_SEC0  : origin = 0x090002, length = 0x000FFE
   FLASH_BANK1_SEC1  : origin = 0x091000, length = 0x001000
   FLASH_BANK1_SEC2  : origin = 0x092008, length = 0x000FF8
   FLASH_BANK1_SEC3  : origin = 0x093000, length = 0x001000
   FLASH_BANK1_SEC4  : origin = 0x094000, length = 0x001000
   FLASH_BANK1_SEC5  : origin = 0x095000, length = 0x001000
   FLASH_BANK1_SEC6  : origin = 0x096000, length = 0x001000
   FLASH_BANK1_SEC7  : origin = 0x097000, length = 0x001000
   FLASH_BANK1_SEC8  : origin = 0x098000, length = 0x001000
   FLASH_BANK1_SEC9  : origin = 0x099000, length = 0x001000
   FLASH_BANK1_SEC10_11    : origin = 0x09A000, length = 0x002000
   FLASH_BANK1_SEC12_13_14 : origin = 0x09C000, length = 0x002FF0
   FLASH_BANK1_SEC15 : origin = 0x09EFF2, length = 0x000FFE

  /* BANK 2 */
   FLASH_BANK2_SEC0  : origin = 0x0A0002, length = 0x000FFE
   FLASH_BANK2_SEC1  : origin = 0x0A1000, length = 0x001000
   FLASH_BANK2_SEC2  : origin = 0x0A2008, length = 0x000FF8
   FLASH_BANK2_SEC3  : origin = 0x0A3000, length = 0x001000
   FLASH_BANK2_SEC4  : origin = 0x0A4000, length = 0x001000
   FLASH_BANK2_SEC5  : origin = 0x0A5000, length = 0x001000
   FLASH_BANK2_SEC6  : origin = 0x0A6000, length = 0x001000
   FLASH_BANK2_SEC7  : origin = 0x0A7000, length = 0x001000
   FLASH_BANK2_SEC8  : origin = 0x0A8000, length = 0x001000
   FLASH_BANK2_SEC9  : origin = 0x0A9000, length = 0x001000
   FLASH_BANK2_SEC10_11    : origin = 0x0AA000, length = 0x002000
   FLASH_BANK2_SEC12_13_14 : origin = 0x0AC000, length = 0x002FF0
   FLASH_BANK2_SEC15 : origin = 0x0AEFF2, length = 0x000FFE

// FLASH_BANK0_SEC15_RSVD     : origin = 0x0AFFF0, length = 0x000010  /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */


   CLA1_MSGRAMLOW   : origin = 0x001480, length = 0x000080
   CLA1_MSGRAMHIGH  : origin = 0x001500, length = 0x000080
   CLA_DMA_RAM      : origin = 0x001680, length = 0x000080
   DMA_CLA_RAM      : origin = 0x001700, length = 0x000080
}


SECTIONS
{
   .cinit           : > FLASH_BANK1_SEC9, ALIGN(4)
   .text            : >>FLASH_BANK1_SEC2 | FLASH_BANK1_SEC3 | FLASH_BANK1_SEC4 | FLASH_BANK1_SEC5 | FLASH_BANK1_SEC6, ALIGN(4)
   codestart        : > BEGIN, ALIGN(4)

   coeff_table      : > FLASH_BANK1_SEC12_13_14,  ALIGN(4)

   .stack           : > RAMM1
   .switch          : > FLASH_BANK1_SEC9, ALIGN(4)

#if defined(__TI_EABI__)
   .init_array      : > FLASH_BANK1_SEC9,       ALIGN(4)
   .bss             : > RAMLS6
   .bss:output      : > RAMLS6
   .bss:cio         : > RAMLS6
   .data            : > RAMLS7
   .sysmem          : > RAMLS7
   .const           : > FLASH_BANK1_SEC9    ALIGN(4)
#else
   .pinit           : > FLASH_BANK1_SEC9       ALIGN(4)
   .ebss            : >>RAMLS5 | RAMLS6
   .esysmem         : > RAMLS6
   .cio             : > RAMLS5
   .econst          : > FLASH_BANK1_SEC9
#endif

   ramgs0           : > RAMGS0
   ramgs1           : > RAMGS1

   .reset           : > RESET,          TYPE = DSECT /* not used, */

   dclfuncs         : > FLASH_BANK1_SEC9,     ALIGN(4)

#if  !(CLA_MATH_TABLES_IN_ROM)
   //
   //Load tables to Flash and copy over to RAM
   //
#if defined(__TI_EABI__)
   CLA1mathTables    :  LOAD = FLASH_BANK1_SEC9,
                        RUN = RAMLS5,
                        RUN_START(CLA1mathTablesRunStart),
                        LOAD_START(CLA1mathTablesLoadStart),
                        LOAD_SIZE(CLA1mathTablesLoadSize),
                        PAGE = 1
#else
   CLA1mathTables    :  LOAD = FLASH_BANK1_SEC9,
                        RUN = RAMLS5,
                        RUN_START(_CLA1mathTablesRunStart),
                        LOAD_START(_CLA1mathTablesLoadStart),
                        LOAD_SIZE(_CLA1mathTablesLoadSize),
                        PAGE = 1
#endif

#endif

#if defined(__TI_EABI__)
    /* CLA specific sections */
    Cla1Prog        : LOAD = FLASH_BANK1_SEC10_11,
                      RUN = RAMLS0_LS1_LS2,
                      LOAD_START(Cla1ProgLoadStart),
                      RUN_START(Cla1ProgRunStart),
                      LOAD_SIZE(Cla1ProgLoadSize),
                      ALIGN(4)
#else
    /* CLA specific sections */
    Cla1Prog        : LOAD = FLASH_BANK1_SEC10_11,
                      RUN = RAMLS0_LS1_LS2,
                      LOAD_START(_Cla1ProgLoadStart),
                      RUN_START(_Cla1ProgRunStart),
                      LOAD_SIZE(_Cla1ProgLoadSize),
                      ALIGN(4)
#endif


    Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW
    CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH

#if defined(__TI_EABI__)
   .TI.ramfunc      : LOAD = FLASH_BANK1_SEC9,
                      RUN = RAMLS5
                      LOAD_START(RamfuncsLoadStart),
                      LOAD_SIZE(RamfuncsLoadSize),
                      LOAD_END(RamfuncsLoadEnd),
                      RUN_START(RamfuncsRunStart),
                      RUN_SIZE(RamfuncsRunSize),
                      RUN_END(RamfuncsRunEnd),
                      ALIGN(4)
#else
   .TI.ramfunc      : LOAD = FLASH_BANK1_SEC9,
                      RUN = RAMLS5
                      LOAD_START(_RamfuncsLoadStart),
                      LOAD_SIZE(_RamfuncsLoadSize),
                      LOAD_END(_RamfuncsLoadEnd),
                      RUN_START(_RamfuncsRunStart),
                      RUN_SIZE(_RamfuncsRunSize),
                      RUN_END(_RamfuncsRunEnd),
                      ALIGN(4)
#endif

   .scratchpad      : > RAMLS3
   .bss_cla         : > RAMLS3

   Cla1DataRam      : > RAMLS4
   cla_shared       : > RAMLS3
   CLADataLS1       : > RAMLS3
   Cla_To_Dma       : > CLA_DMA_RAM
   Dma_To_Cla       : > DMA_CLA_RAM


#if defined(__TI_EABI__)
   .const_cla      : LOAD = FLASH_BANK1_SEC2,
                      RUN = RAMLS4,
                      RUN_START(Cla1ConstRunStart),
                      LOAD_START(Cla1ConstLoadStart),
                      LOAD_SIZE(Cla1ConstLoadSize),
                      ALIGN(4)
#else
   .const_cla      : LOAD = FLASH_BANK1_SEC2,
                      RUN = RAMLS4,
                      RUN_START(_Cla1ConstRunStart),
                      LOAD_START(_Cla1ConstLoadStart),
                      LOAD_SIZE(_Cla1ConstLoadSize),
                      ALIGN(4)
#endif
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

    The Kernel plus bank select code is located in BANK0 and has this linker Config

    //
// Keep the _bankSelect symbol
//
-u bankSelect

MEMORY
{
   BEGIN           	: origin = 0x00080000, length = 0x0000004c
   BOOT_RSVD		: origin = 0x00000002, length = 0x00000126

   RAMM0           	: origin = 0x00000128, length = 0x000002D8
   RAMM1            : origin = 0x00000400, length = 0x00000380     /* on-chip RAM block M1 */
   BOOT_RSVD_SYSBIOS: origin = 0x00000780, length = 0x00000080

   RAMLS0           : origin = 0x00008000, length = 0x00000800
   RAMLS1           : origin = 0x00008800, length = 0x00000800
   RAMLS2           : origin = 0x00009000, length = 0x00000800
   RAMLS3           : origin = 0x00009800, length = 0x00000800
   RAMLS4           : origin = 0x0000A000, length = 0x00000800
   RAMLS5           : origin = 0x0000A800, length = 0x00000800
   RAMLS6           : origin = 0x0000B000, length = 0x00000800
   RAMLS7           : origin = 0x0000B800, length = 0x00000800
   
   RAMGS0           : origin = 0x0000C000, length = 0x00001000
   RAMGS1           : origin = 0x0000D000, length = 0x00001000
   RAMGS2           : origin = 0x0000E000, length = 0x00001000
   RAMGS3           : origin = 0x0000F000, length = 0x00001000

   BOOTROM          : origin = 0x003F8000, length = 0x00007FC0
   SECURE_ROM       : origin = 0x003F2000, length = 0x00006000

   RESET            : origin = 0x003FFFC0, length = 0x00000002

   /* Flash sectors */

   //
   // Allocate space for the liveDFU function in bank 0
   //
   BANK0_SEC1        : origin = 0x081000, length = 0x000017
   /* BANK 0 */
   FLASH_BANK0_SEC0  : origin = 0x08004C, length = 0x000FB4
   FLASH_BANK0_SEC1  : origin = 0x081017, length = 0x000FE9
   FLASH_BANK0_SEC2  : origin = 0x082000, length = 0x001000
   FLASH_BANK0_SEC3  : origin = 0x083000, length = 0x001000
   FLASH_BANK0_SEC4  : origin = 0x084000, length = 0x001000
   FLASH_BANK0_SEC5  : origin = 0x085000, length = 0x001000
   FLASH_BANK0_SEC6  : origin = 0x086000, length = 0x001000
   FLASH_BANK0_SEC7  : origin = 0x087000, length = 0x001000
   FLASH_BANK0_SEC8  : origin = 0x088000, length = 0x001000
   FLASH_BANK0_SEC9  : origin = 0x089000, length = 0x001000
   FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000
   FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000
   FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000
   FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000
   FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000
   FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000

   /* BANK 1 */
   FLASH_BANK1_SEC0  : origin = 0x090000, length = 0x001000
   FLASH_BANK1_SEC1  : origin = 0x091000, length = 0x001000
   FLASH_BANK1_SEC2  : origin = 0x092000, length = 0x001000
   FLASH_BANK1_SEC3  : origin = 0x093000, length = 0x001000
   FLASH_BANK1_SEC4  : origin = 0x094000, length = 0x001000
   FLASH_BANK1_SEC5  : origin = 0x095000, length = 0x001000
   FLASH_BANK1_SEC6  : origin = 0x096000, length = 0x001000
   FLASH_BANK1_SEC7  : origin = 0x097000, length = 0x001000
   FLASH_BANK1_SEC8  : origin = 0x098000, length = 0x001000
   FLASH_BANK1_SEC9  : origin = 0x099000, length = 0x001000
   FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000
   FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000
   FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000
   FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000
   FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000
   FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x001000

  /* BANK 2 */
   FLASH_BANK2_SEC0  : origin = 0x0A0000, length = 0x001000
   FLASH_BANK2_SEC1  : origin = 0x0A1000, length = 0x001000
   FLASH_BANK2_SEC2  : origin = 0x0A2000, length = 0x001000
   FLASH_BANK2_SEC3  : origin = 0x0A3000, length = 0x001000
   FLASH_BANK2_SEC4  : origin = 0x0A4000, length = 0x001000
   FLASH_BANK2_SEC5  : origin = 0x0A5000, length = 0x001000
   FLASH_BANK2_SEC6  : origin = 0x0A6000, length = 0x001000
   FLASH_BANK2_SEC7  : origin = 0x0A7000, length = 0x001000
   FLASH_BANK2_SEC8  : origin = 0x0A8000, length = 0x001000
   FLASH_BANK2_SEC9  : origin = 0x0A9000, length = 0x001000
   FLASH_BANK2_SEC10 : origin = 0x0AA000, length = 0x001000
   FLASH_BANK2_SEC11 : origin = 0x0AB000, length = 0x001000
   FLASH_BANK2_SEC12 : origin = 0x0AC000, length = 0x001000
   FLASH_BANK2_SEC13 : origin = 0x0AD000, length = 0x001000
   FLASH_BANK2_SEC14 : origin = 0x0AE000, length = 0x001000
   FLASH_BANK2_SEC15 : origin = 0x0AF000, length = 0x001000


}


SECTIONS
{
   codestart        : > BEGIN, ALIGN(8)
   .text            : >> FLASH_BANK0_SEC0 |FLASH_BANK0_SEC1 ,   ALIGN(8)
   .cinit           : > FLASH_BANK0_SEC1,  ALIGN(8)
   .switch          : > FLASH_BANK0_SEC0,  ALIGN(8)
   .reset           : > RESET,                  TYPE = DSECT /* not used, */

   .stack           : > RAMM1

#if defined(__TI_EABI__)
   .init_array      : > FLASH_BANK0_SEC0,  ALIGN(8)
   .bss             : > RAMLS5
   .bss:output      : > RAMLS3
   .bss:cio         : > RAMLS0
   .data            : > RAMLS5
   .sysmem          : > RAMLS5
   .const           : > FLASH_BANK0_SEC0,  ALIGN(8)
#else
   .pinit           : > FLASH_BANK0_SEC0,  ALIGN(8)
   .ebss            : > RAMLS5
   .esysmem         : > RAMLS5
   .cio             : > RAMLS0
   .econst          : > FLASH_BANK0_SEC0,  ALIGN(8)
#endif

    ramgs0 : > RAMGS0
    ramgs1 : > RAMGS0

   .TI.ramfunc      : LOAD = FLASH_BANK0_SEC0,
                      RUN = RAMLS0,
                      LOAD_START(RamfuncsLoadStart),
                      LOAD_SIZE(RamfuncsLoadSize),
                      LOAD_END(RamfuncsLoadEnd),
                      RUN_START(RamfuncsRunStart),
                      RUN_SIZE(RamfuncsRunSize),
                      RUN_END(RamfuncsRunEnd),
                      ALIGN(8)

   LDFU_BANK0        : > BANK0_SEC1,     ALIGN(8)

}

    As I have explained, when finishes flashing the new program, as the LEDs turn off so I assume that 

    the watchdog provokes the reset, but it doesn't start the new program and the processor becomes halted

    If I turn off and on the microcontroller, then starts working OK

    Regards,

    Fernando

  • 0 in reply to Fernando Gatto
    TI__Mastermind 28255 points

    Fernando,

    Let me look into this issue and get back to you. 

    Thanks,

    Sira

  • 0 in reply to Sira Rao80
    TI__Mastermind 28255 points

    Fernando,

    Please provide some details:

    Where did you obtain the SCI Flash kernels for F28003x that you used as the starting point for your development? The correct kernels to be used are located within the DigitalPowerSDK v4.01.00.00 in the examples folder of the TIDM-02011 solution.

    C2000Ware_DigitalPower_SDK_4_01_00_00\solutions\tidm_02011\f28003x\examples\flash

    There are some differences in the projectspec as well as flash_kernel_ex3_ldfu.c between the above release, and what is in C2000Ware v4.01.

    Additionally, you will need to define the macro LFU_WITH_RESET in flash_kernel_ex3_ldfu.c, and this will trigger the watchdog. By default, the example is setup to run LFU without a device reset.

    So please use the Flash kernel from the DigitalPowerSDK v4.01 and not C2000Ware v4.01.

    Thanks,

    Sira

  • 0 in reply to Sira Rao80
    Intellectual 360 points

    Sira,

    Thanks for your help. I have used the examples that are inside C2000Ware v4.01, so I will check the example that you mention inside DigitalPowerSDK v4.01

    Regards,

    Fernando

  • 0 in reply to Fernando Gatto
    TI__Mastermind 28255 points

    Fernando, sounds good, please keep me posted.

    Thanks,

    Sira

  • 0 in reply to Sira Rao80
    Intellectual 360 points

    Hi again:

    I have included all the changes in the updated example you mentioned. It still does the same. When it finishes flashing the new program, it gets frozen.


    One particular thing is that I am starting the Update process just right after flashing the kernel using the JTAG and without turning off and on the device.

    If after flashing the Kernel with the Jtag I turn on and off the device and then I run the update process, the microcontroller resets Ok. The new program

    starts running properly. Probably this fact could give you some clue of what is happening.

    Regards,

    Fernando

                    

  • 0 in reply to Fernando Gatto
    TI__Mastermind 28255 points

    Fernando,

    I am a little confused about exactly the problem scenario in your case. So let me describe the steps that work for me (serial/SCI will be replaced with CAN in your case):

    1. Build the Flash kernel with LFU_WITH_RESET (both LDFU_BANK0 and LDFU_BANK1 build configurations)

    2. Use CCS to Flash the SCI Flash kernel LDFU_BANK0 to Bank0. Execution goes to the bankSelect() function. Hit Run. Then use a command prompt to issue a serial flash programmer command with the desired Application file (targeted to Bank1). The command menu comes up. Issue LFU command (8). The App is programmed to Bank1.

    3. Disconnect the target. Use a different target configuration file (ccxml) that erases only Necessary Flash sectors. Connect to the target, and use CCS to Flash the SCI Flash kernel LDFU_BANK1 to Bank1. Execution goes to main(). Hit Run. Then use a command prompt to issue a serial flash programmer command with the desired Application file (targeted to Bank0). The command menu comes up. Issue LFU command (8). The App is programmed to Bank0.

    4. Disconnect the target. Now both Flash banks have Flash kernel and Apps.

    5. Reset the device. App on Bank0 is now active.

    6. Now you can use a command prompt to issue a serial flash programmer command with the desired Application file (targeted to Bank1). The command menu comes up. Issue LFU command (8). The App is programmed to Bank1. WD reset will automatically occur and App on Bank1 will automatically start running. Now you can repeat this ping-pong step as many times as you want to, without having to use CCS or manually reset the device.

    Thanks,

    Sira

  • 0 in reply to Sira Rao80
    Intellectual 360 points

    Hi Sira,

                Thanks for your help.

    I was expecting that the application starts running directly after executing step 2, without applying a reset.

    But it only starts if I turn off and on the device after finishing this second step.

    If I reset the microcontroller after flashing the kernel and before loading the application into the BANK1, 
    then once it finishes the flashing process through CAN, the program starts running directly.

    I hope that this explains what I was expecting. If there is no way of avoiding this reset, it is OK and we will take into account

    for the manufacturing process

    Regards

  • 0 in reply to Fernando Gatto
    TI__Mastermind 28255 points

    Fernando,

    Ok, now I understand.

    I think this happens because in Step 2, you've connected the debugger and so when the WD reset occurs, execution goes to the Boot ROM, where it identifies that the debugger is connected, so it will not Boot to the usual Flash boot entry point.

    If you read 4.6.2 of the F28003x TRM, it has some associated details.

    If you reset the device after programming the Flash kernel, the debugger is disconnected, so if you run an LFU command and program the App, then the WD reset occurs, Boot ROM boots to the Flash boot entry point (bankSelect()), and your App will run.

    Thanks,

    Sira