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Original question:

TMS320F280049C: CMPSS - Ramp Generator Prescaler

TMS320F28388D: CMPSS compensation ramp slope for lower switching frequencies

Sandro Margeta
Prodigy 50 points
Part Number: TMS320F28388D

Dear TI experts, 

Please correct me if I am wrong, but after consulting with documentation, I've concluded that the slowest falling time of CMPSS compensation ramp Is 1 LSB every 16 SYSCLK.

It means that with the 200 MHz SYSCLK, the ramp (DAC output) will from the maximum value fall to zero in just 327,6  μs, which makes it inapplicable for switching frequencies below ~3 kHz (and for those frequencies close to the minimum we can only use DECVAL of 1, i.e only one slope setting).

I am curious if there is any way to slow down the ramp descent below 1 LSB every 16 SYSCLK (e.g 1 LSB every 32 SYSCLK) so we can utilize more decrement values for switching frequencies of 4 kHz in our systems.

Kind regards, 

Sandro

  • +1
    TI__Guru* 80520 points

    Sandro,

    I don't see a straightforward option here with the ramp generator, as you mention the ramp generator is clocked directly from SysClk. 

    This may not be ideal, but if you have some lower utilization on the 2nd core, you could clock it at a frequency less than 200MHz to decrease the SYSCLK passed to the CMPSS block.

    Another option would be to use the CPU or DMA to manually write the DAC value to create the slower ramp output that is needed.  DMA could be triggered to write at known intervals based on a PWM trigger.

    Best,

    Matthew