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TMS320F28335: Clarify some setting usage in Uniflash

Wayne Huang
Genius 16795 points
Part Number: TMS320F28335
Other Parts Discussed in Thread: UNIFLASH

Dear Champs,

I am asking this for our customer.

Because there is something wrong with flash programming in the user's production line, the user wants to ensure every setting in our Uniflash is right.

In Uniflash Settings and Utilities, 

1) What is below setting "clock configuration" used for? If the user uses a 20-MHz external crystal, should the user set below as 20 x 10 / 2 = 100 MHz? 

As F28335 can run up to 150 MHz, but PLLCR max is 10 here.

How do we use the below settings to get 150 MHz?

2) What is below "Frequency Test" for?

  • 0
    TI__Guru* 87155 points

    Hi Wayne,

    I assigned this to our F28335 expert.  Please expect a reply early next week.

    Thanks and regards,
    Vamsi

  • 0 in reply to Vamsi Gudivada
    TI__Guru* 82230 points

    Wayne,

    The PLLCR register is capped at value of 10 per the TRM.  So this is the max PLL multiplier available to the customer.  In this case, the highest system clock that the customer can realize would be 20MHz x 7(PLLCR)/1(CLKINDIV)  = 140MHz.  They can use this setting in Uniflash as well.

    The toggle test outputs a derivative of SYSCLK on the GPIO that is picked from the drop down.  This is recommended to use during development to ensure that the PLL settings are getting the expected output clock before programming.  I think the output should be 10kHz, but I'm not sure if the uniflash version will auto-correct for different sysclks that 150MHz or not.

    Once customer is confident in the clock settings there is no need to run this test prior to programmation.

    Best,
    Matthew

  • 0 in reply to MatthewPate
    TI__Genius 16795 points

    Dear Matt,

    ”  I think the output should be 10kHz, but I'm not sure if the uniflash version will auto-correct for different sysclks that 150MHz or not.”

    I am not very clear about the above. Would you please make it clearer?

    If the user sets 20 MHz x 7 (PLLCR) / 1 (CLKINDIV) = 140 MHz in the clock configuration of the Uniflash Settings, what is the relationship between this 140 MHz and the GPIO frequency test?

    Wayne Huang

  • 0 in reply to Wayne Huang
    TI__Guru* 82230 points

    Wayne,
    I need to check with the Uniflash owners how they implemented this.  When the standalone API is used, this should stay at 10kHz/autoscale with the changing SYSCLK changes.

    Best,

    Matthew

  • +1 in reply to MatthewPate
    TI__Guru* 82230 points

    Wayne,

    Based on what I've found out I think this should be 10kHz no matter the clock settings, i.e. the code should self adjust the delay loops to keep this constant.

    Best,

    Matthew