TMS320F28027: Accuracy and maximum sampling rate for integrated DAC

Hi Ernest,

Ernest Yong said:

1. May I check with you what is the maximum sample rate for the DAC used be the comparator? I tried looking into the data sheet (Section 9.9.1.3.1) but it seems like there is no clear explanation... 

The DAC is a 10-bit DAC. The ramp will generate a value that changes every SYSCLK. This value is used as the "negative" terminal input of the comparator. 

Ernest Yong said:

2. Is there any TI DSP with better or more accurate ramp generator?

I cannot speak to other TI products, but for C2000 devices, I would recommend looking at the F28002x class of devices.

Snippet below from the "TMS320F2802x/TMS320F2803x to TMS320F28002x Migration Overview" app report

"The F28002x CMPSS provides substantial enhancements over the simple analog comparator with the integrated 10-bit reference digital-to-analog (DAC) circuits found on the F2802x/03x devices. There are four CMPSS modules available on the F28002x devices. Each module contains two comparators, two reference 12-bit DACs, two digital filters and one ramp generator. The CMPSS modules are useful for implementing peak current mode control and voltage trip monitoring, which are used in applications such as switched-mode power control and power factor correction. The module is designed around a pair of analog comparators which generates a digital output indicating if the voltage on the positive input is greater than the voltage on the negative input. The positive input to the comparator is always driven from an external pin. The negative input can be driven by either an external pin or an internal programmable 12-bit DAC as a reference voltage. Values written to the DAC can take effect immediately or be synchronized with ePWM events. A falling-ramp generator is available to control the internal DAC reference value for one comparator in the module, which enables peak current mode control in digital power applications. Each comparator output is fed through a programmable digital filter to prevent electrical switching noise from causing spurious trip signals. The output of the CMPSS generates trip signals to the ePWM event trigger submodule and GPIO structure. Additionally, the CMPSS features PWM blanking capability to clear-and-reset existing or imminent trip conditions near the ePWM cycle boundaries. Also, by using the analog subsystem interconnect scheme the CMPSS comparator positive and negative input signals are independently selectable."

Best Regards,

Marlyn

Hi Marlyn, 

Thanks for your reply, what about the sampling rate of this 10-bit DAC?

Hi Ernest,

I do not believe we categorize this. Let me check with others in my team. I will respond back by tomorrow.

Best Regards,

Marlyn

Hi Ernest,

This will come from the DAC settling time. Please refer to the DAC settling time figure within the datasheet. Depending on the DAC step size (change between DAC output values) and how many codes you want to settle within there will be a different DAC settling time.

Best Regards,

Marlyn