TMS320F28035 ADC "just in time" EOC timing CLA task

the same as the previous post with the waveforms

My application is a resonant DCDC converter. I'm using "just in time" adc sampling with CLA TMS320F28035.

The CLA task should always start in the middle of the EPWM3A on time, but when the circuit is powered, sometimes it works as expected and after some POWER ON / POWER OFF cycles the The start  of CLA task is shifted to right (instead of start in the middle of the EPWM3A "ON TIME", it starts in the end of the EPWM3A "ON TIME").

someone has experienced that behaviour?

some idea to solve that issue?

Thanks in advance,

Ricardo

see waveforms in the end of this post

system description (main code lines for reference):

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EPWM3A - Half-Bridge High-Side PWM signal

EPWM3B - Half-Bridge Low-Side PWM signal

ADCINA3 - OUTPUT VOLTAGE SAMPLE

  AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 0x9;                 // ADCS0CA event connected to ePWM3A
  AdcRegs.ADCSOC1CTL.bit.CHSEL = 3;                        // ADCINA3 selected to SOC1

The PWM register are loaded according to the following:

EPwm3Regs.TBPRD= prd

EPwm3Regs.CMPA.half.CMPA = prd / 2

EPwm3Regs.CMPB = prd / 4

 EPwm3Regs.ETSEL.bit.SOCASEL = ET_CTRU_CMPB; //  SOCA on counter equal to CMPB when the timer is incrementing.

 EPwm3Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group

 EPwm3Regs.ETPS.bit.SOCAPRD = ET_1ST; // Trigger on every event

 SOCA  is trigged by EPWM3 When CMPB is equal to TBPRD / 4 which results in the start of conversion in the midle of the ON time of the switch connected to EPWM3A

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 AdcRegs.ADCCTL1.bit.INTPULSEPOS = 0;  // INT pulse generation occurs when ADC begins conversion

 AdcRegs.INTSEL1N2.bit.INT1CONT = 1;      // ADCINTx pulses are generated whenever an EOC pulse is generated irrespective if the
                                                                                // flag bit is cleared or not.

 AdcRegs.INTSEL1N2.bit.INT1SEL = 0x01;   // EOC1 is trigger for ADCINTx

 AdcRegs.INTSEL1N2.bit.INT1E = 1;              // ADCINTx is enabled

 ADCINA3 (SOC1) is configured to send EOC Early Interrupt Pulse in order to trigger CLA task 1

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 Cla1Regs.MPISRCSEL1.bit.PERINT1SEL = CLA_INT1_ADCINT1;

CLA task 1 is responsible for :

-  READ ADCRESULT

- CONTROL LAW 2P2Z 

-  PWM REGISTER UPDATE

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in order to check the moment when CLA task 1 starts comparator 2 is being used to clear (0) pin 61

in order to check the moment when CLA task 1 stops comparator 2 is being used to set (1) pin 61

using the resource described above is possible to check the EPWM3 signals the BEGIN and the END of CLA task 1

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yellow waveform (falling edge) - begining of CLA task

yellow waveform (low level) - CLA task execution time

yellow waveform (rising edge) - end of CLA task

pink waveform - EPWM3A

blue waveform - EPWM3B

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the waveform below shows the correct operation, the start of CLA task is alligned in the middle of EPWM3A (High Level)

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the waveform below shows the wrong operation, the start of CLA task is shifted to right insted of being alligned in the middle of EPWM3A (High Level)

ricardo,

It looks like you have a pretty good system working and from a quick check-over everything looks fine with your configuration.

How often do you see the issue occur?  Is it correct 99% of the time and about 1% of the time it is incorrect or is it worse than that, etc?

Are any other CLA tasks being used?  If so then the CLA would need to finish any previously started tasks before it can start CLA task 1.  Also, are you using any other of the ADCs?  If other ADCs are being used they could already be queued to convert when your ADC sample comes in.  It may be worthwhile to remove any other ADC conversions temporarily to see if this is the cause.  If this ends up being the issue you can use SOC priority bits to make sure the ADC SOC1 gets priority.


Good luck,
Brett