TMS320F28388D: ePWM as one-shot

I've read the threads about using AQCTLB shadowing to generate a one shot. But if I've got this right, this would juist manipulate the way the PWM outputs would react to the counter, comparator or other signals. The counter would start counting up after it has reached zero anyway. However, this behaviour is already established by the way we trimmed SYNC0 period to the PWM Period. As we use u/d mode and toggle the outputs (deadband mode) at CTR=CMPA we do have stable output when the counter restarts counting up until it reaches CMPA again. But this would never happen before the next SYNC0 from the ESC would reset the counter to zero. So if I'm right there would be no benifit from using the shadowing method to force the output to only one-shot.

Hello,

The simplest way I can think of to generate a one-shot ePWM signal from an external trigger would be to use the Configurable Logic Block (CLB) tool. In fact, there's an example on how to do just that in the CLB user guide! In your C2000 root folder, navigate to 'utilities' -> 'clb_tool' ->'clb_syscfg' -> 'doc' -> 'CLB Tool Users Guide'. In that guide, along with an introduction to using the tool if you need it, section 5.8 discusses the CLB's example 17, One-Shot PWM Generation, with one of the operating modes relying on an external trigger signal.

If you want to adapt the techniques used in the example, I'd suggest taking a look at the SysConfig options selected in the example and determining which ones you need to use and which ones aren't needed by your application.

(Note: In the CLB Users Guide, the f28004x device is specifically referenced- in your case, you'd be replacing that with f2838x, the device you're using. Further information regarding the CLB can be found in numerous places, including a basic tutorial in the C2000 Academy, video tutorials in the TI Training dropdown at the top of the page, and more specific architecture information in your device's TRM.)

Hope I was able to help,

Jason Osborn

Hi Jason,

Thanks so much for this very fast reply. We were thinking of using other features of the MCU to emulate the ePWM section. But we dropped this idea because we are using several other advanced features of the ePWM. As we are designing a servo drive, we are happy to have features like configurable RED / FED times for solving the deadband task. We also need to trigger an ISR with the PWM signal edge but delayed by the FED time to start several ADC conversions out of EMI zone. Thgis is also the reason to use up/down couunting with value comparation to adjust the pulse width: Using 3 PWMs in parallel and synchronized, we use this method to seperate the switching edges of all three driver outputs (results in reduced EMI problems) and still synchronize them (just phase shifting).

Emulating all these features with CLB would be like reconstructing the mighty ePWM just to get the oneshot feature. So we would rather stay with the idea to use ePWM and loose 20 ns of maximum duty cycle for the safety margin of differing SYNC0 to TBPRD periods.

Any other idea?

This is how things would look with oru actual solution. Should work but having the counter restart counting up before the next SYNC0 comes from ESC is kind of "ugly". If there, e.g., would be no SYNC0 because of an error (ESC state machine stops syncing) the ePWM would generate further pulses until some kind of error detection and reaction routine would stop the ePWM. We would prefer an immediate and automatic stop of output pulses if no SYNC0 comes from ESC. So having the SYNC0 as trigger for a oneshot pulse (but still having delayed trigger for ADC ISR etc. and having configurable RED/FED) would be perfect. But I can't see a way to get this done.

EDIT: See my next reply- although the method described below should work, I believe, there's a significantly more intuitive, well-documented way to do this utilizing the AQ module's external trigger.

Ah, I see what you're asking now, my apologies. In this case, I believe the first answer I would see would be to use the Trip Zone module. With the right settings, it should be possible to set the one-shot trip (OST) condition to force EPWMxA/B low. Then, your external signal can be set to do two things- generate a trip zone interrupt which clears the OST trip flag which re-enables EPWMxA/B, and also acting as the sync signal to set the counter to zero. Finally, you would need to set the CTR=Zero signal to generate an interrupt which re-sets the OST condition, forcing the signal low once again at the end of the single cycle.

Alternatively, we could look at the CLB once more, which can be configured to force the ePWM signals low in the initial state, pass-through the ePWM signals in the second system state (triggered by your external signal), and then return to the initial state after one ePWM cycle. Once more, your signal needs to act as the synch signal to ensure the counter is where you need it to be, but overall, this may be a more reliable route so long as you're willing to go through the CLB to do it.

Hope that made sense, and always feel free to ask more clarifying questions,
Jason Osborn

(As an aside, I'm uncertain if the CTR=Zero signal triggers when when the counter is reset to zero by the synchronization. If so, I'd personally just set that interrupt to ignore the first time it triggers in the software.}

Hello,

I've just realized I missed a significantly easier answer than what I prev. suggested- my apologies! If you go through the C2000Ware examples for your device, the ePWM_ex12_monoshot_mode should be exactly what you're looking for- a single-shot of the ePWM in response to an external signal!

Again, my apologies for missing this in my initial replies.

Hope this helps,

Jason Osborn

Hello Jason,

please try to understand the applications's needs as explained before:

We are designing a modular servo drive with 3 axes per module.

The modules are synchronized to +/- 10 ns over the "dsitributed clock" (=DC) feature of EtherCAT network.

Each ESC (EtherCAT slave controller) of the TMS2838 is running its own but globally snchronized clock which generates so called SYNC0-signals.

Our SYNC0 period is 32.25 µs. The DC is the only method to synchronize multiple TMS2838 to the ns over a network cable.

SYNC0 is origically met to trigger in- or output latches of digital IOs.

In our case (servo drive) it needs to synchronize PWM pulses to excately synchronize multiple axes.

As I've mentioned in this thread, there are EMI-reasons to reduce simultaneous edges of multiple PWM outputs.

So the pulse synchronization is made to the pulse midth where no edges occur.

If look carefully at the diagram I've posted, you will see the edges of OUTA/OUTB are symetrically around the midth of the counter period (which is nearly the same as the SYNC0 period).

So we do not only change the pulse width for each controller cycle (it's a closed loop current controller), but we also shift the phase.

This reduces the probability of simultanious pulse edges over the whole system.

So there is no chance to switch on the pulse by the "external" signal SYNC0 (which is b.t.w. internal to the TMS2838).

The time between cycle start (SYNC0) and OUTA/OUTB edge differs each cycle and depends on the PWM CMPA value.

I hope you understand that the ePWM_ex12_monoshot_mode does not work for us.

All the solutions for oneshot action I've read so far suffer from the root:

TI should simply implement a oneshot counter mode just like up, down, up/down and freeze.

But TI recommends to either implement ePWM-logic with CLB or to use ePWM features (invented for other reasons) in a complex way.

Doing so results in loosing importent ePWM faetures (up/down mode, deadband switching, etc.).

So to avoid the wrong signal generation in case of a SYNC0 loss (e.g. ESC state machine has changed state),

we rather prefer to start a timer-window on CTR=zero and trigger a monoflop TRIPzone (switching OUTA/B off) if no SYNC0 happens inside this window.

So we would allow the CTR to restart couting up from zero but would not allow the CTR=CMPA to set the OUTA/B if no SYNC0 has been received.

Greetings,

Volker.

Hello Volker,

Another TIer and I are currently looking into this problem, and we should be able to get back to you with another approach by the end of day Friday. In the meantime, I will note that usage of the CLB does not necessarily lose ePWM features- the CLB is able to 'hijack' inputs and outputs to a variety of ePWM submodules to manipulate the signals in question, and usage of that functionality is what I had been suggesting in my second reply- manipulation of the ePWM's final output after having already passed through all ePWM submodules.

At any rate, we will continue to look into this for you, and hopefully we'll find a satisfactory solution.

Regards,

Jason Osborn

Hello Jason,

sorry for my late reply but I've been on vacation the last 2 weeks. Thanks for your last suggestion. I can see the way you suggested to block the ISR by using a CLB statemachine between the Counter Compare Signal and the Event Trigger module. CLB would only bypass the Counter Compare Signal to the Event Trigger Module if there has been a SyncSignal since the last Trigger. So far so good. But I have not yet understood the way you can supress the Dead Band  Module to change ePWMA/B outputs. The DB is triggered by the AQ. AQ is (in my actual suggestion) fired by CC CTR=CMPA. I can't see a way to stop CC from inserting its CTR=CMPA signal to the AQ module as the Aq (other than the ET) does not seem to have an Digital Compare Input which could be used by a CLB statemachine. So how can we stop the counter from firing the AQ/DB? Or would you see a possibility to use the TZ to freeze the outputs in case of a CLB statemachine detecting a CNT=CMPA without prior SYNC0 ?