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TMS320F28379D: ramp compensation for peak current mode control

Himansu Sahoo
Prodigy 20 points

Part Number: TMS320F28379D

Hi experts,

I am trying to implement the ramp compensation logic along with the peak current mode control concept on a boost derived converter. I have gone through the available documents, but not able to get a clear understanding. i have confusion regarding the use of resisters like "RAMPMAXREFS","RAMPDECVALS'. As per my understanding the output of controller will be feed to the RAMPMAXREFS register and the value of RAMPDECVALS will be subtracted from this at each system clock.  

How to choose the values for these registers ?

Does it required to use CLA to implement this concept ? or Can it be done only by just assigning required values to the above said registers with out a need of any calculation required by CLA ?

  • 0
    TI__Mastermind 24121 points

    Hi Himansu,

    Let me transfer this to one of our systems experts, they were out of office yesterday

    Regards,

    Peter

  • +1
    TI__Genius 12225 points

    No CLA is needed for this. 

     The process is explained below:

    The peak current reference command is written to the C2000 MCU register RAMPMAXREFS which is the starting value of the RAMP used for slope compensation. The slope is decided by the value written in the register RAMPDACVALS. The ramp generator produces a falling-ramp input for the high reference 12-bit DAC when selected. Note that in this mode, the reference 12- bit DAC uses the most significant 12 bits of the RAMPSTS countdown register as its input. The low 4 bits of the RAMPSTS countdown register effectively act as a prescaler for the falling-ramp rate configurable with RAMPDECVALA. The slope value is chosen to ensure the fastest inner peak current control loop, and hence a faster outer voltage control loop, while eliminating any possibility of subharmonic oscillations.

    The slope value used in such a DC/DC design using C2000 MCU can be explained in the following way.

    For the C2000 MCU the internal DAC is 12bit. But the actual DAC input register (RAMPMAXREFA) is 16bit. So the max input value for the DAC is 0xFFFF = 65535. This corresponds to 3.3V at the DAC output.

    For a CPU clock frequency (fCPU) of 100MHz and a slope value of m, the DAC output voltage will drop at a rate of R, where R is given by,

    R = m*{(3.3/65535)/(1/fCPU)} = m*{(3.3/65535)/(1/100x106 )} volts/Sec

    If m = 20 (m can be any value between 0 to 255), then, R = 20*{(3.3/65535)/(1/100x106 )} = 100710 volts/Sec = 0.10071 volts/uS.

    For a specific load power if the ON time (power transfer time) is Td (in uS) in every half of the primary side PWM cycle (fPWM), then assuming the sampling cycle the same as the PWM cycle, the DAC value will decrease from its initial written value by an amount of ΔV = (R)*(Td) If the measured peak current sense voltage is Vcs, then the commanded DAC value (from the voltage controller output written into the DAC input) represents a voltage of: U = Vcs + ΔV Because of slope compensation this value decreases by ΔV during the ON time Td and the final DAC output matches the peak feedback current sense voltage Vcs.

    Also, we have the TIDM-2000 reference design that has the code for PCMC PSFB DC/DC

    Shamim