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TMS320F28x Write Enable low for 2 clock cycles

Newton
Expert 1125 points

Does  TMS320F28x family DSP has a capability of keeping the Write Enable low for 2 consecutive clock cycles ?

The reason for this question is we are trying to write/configure  FPGA using TI DSP.

TMS320F28x DSP does only non-continuous data transfer. It has to write  a  sync word, which is a 32-bit word.

The FPGA requires that CSI_B is not deasserted during the sync word write.

 

However, for 16-bit mode it takes 2 writes to transfer the sync word with CSI_B being deasserted. The sync word is not being recognized and the configuration cannot be successful

 

regards

  • 0
    TI__Guru* 82681 points

    Hi Himansu,

    You are using the XINTF, correct? Which F28x device are you looking at (281x/283x?) - these have slightly different XINTF modules. There is an FAQ for the different XINTF modules here:

    From the FAQ:

    Q: Will the chip select line stay low during back-to-back accesses to the same zone?

    Yes. Although keep in mind all accesses begin on the rising edge of XCLKOUT. For this reason, if there is a divider between XTIMCLK and XCLKOUT and the access ends on the falling edge of XCLKOUT, then there will be alignment cycle(s) between back-to-back reads where the chip select will go high. This alignment to wait for the next rising edge of XCLKOUT to start the next access.

    So at the moment you may be running into a problem of your access ending on the falling edge of XCLKOUT. Or, if you have 32 data lines connected and are performing two consecutive accesses to different zones, that is your problem. The solution to this is on a 283x device to configure it for 32 bit mode (see section 2.7 in the XINTF guide).

    One other thing  you may want to consider:

    If you need to you may want to simply control the chip select line in software - you can do this on 283x devices by configuring it as a GPIO, then adding your code to make the line go high/low at the appropriate places in your transfers.

    Regards,

    Katie

  • 0 in reply to Katie Pier
    Prodigy 140 points

    Hi Katie, Himansu,

    Yes, we are using the XINTF interface on the 2812 processor. The interface requirement to the FPGA are to deliver 32 bit 'Sync' word without the CS line of the FPGA going high. The caveat being that when the CS is low, the FPGA is expecting data on every rising edge of the clock. The closest I've come to meeting this requirement is having the DSP CS low for 3 XCLKOUT cycles, with 2 ~WE enables low for 1 XCLKOUT cycle with a 1/2 XCLKOUT cycle where ~WE is high as data changes. So, I think the real requirement is there a configuration where the DSP can output data on consecutive clocks edges?

    Here's out current configuration.

    SYSCLK = 60MHz; XTIMCLK = 30Mhz; XCLKOUT = 15Mhz

    Lead = 1; Active = 0; Trail = 0

    Write Buffering = 3

    Thanks,

    Neil


  • 0 in reply to nwillard
    TI__Guru* 82681 points

    Hi Himansu,

    I'm a little confused because we've gone back and forth between talking about Chip Select and Write Enable. Is it XWE or XCSZx that you are needing to stay low between your two writes to your FPGA?

    Regards,

    Katie

  • 0 in reply to Katie Pier
    Prodigy 140 points

    Hello Katie,

    The chip select (CSI_B) that Himansu is referring to is from the FPGA perspective. The ~WE of the DSP is conencted to the CSI_B of the FPGA. The requirement is still that the DSP must present valid data every XCLKOUT  (at least for 1 32-bit word, 2 clks).


    Thanks,

    Neil

  • 0 in reply to nwillard
    TI__Guru* 82681 points

    Hi Neil & Himansu,

    Thanks for the clarification - ignore my earlier comments about "chip select" - I was referring to the c2000 XCSZx signals in that case, whereas you are concerned with the write enable.

    We only guarantee that the write data is valid after the lead cycle is completed, and the minimum lead time is in your case 1/2 xclkout, or 1 xtimclk cycle. This is why the write enable pin will always be high during the lead time. You could potentially use a pin as a GPIO instead of the XWE signal to keep that FPGA CSI_B held low in software between the two write accesses, but we won't be able to guarantee that the data on the lines will be valid during that lead cycle of 1/2 xclkout (where the xclkout line is high). So you'll have to look at the timing for your FPGA device and when exactly it actually latches in the data in relation to the timing of the xintf and perhaps experiment a little to see if this would possibly work in your case - but no promises.

    Regards,

    Katie