• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 82 subscribers
  • Views 840 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28069 - RXFFIENA, RX/BK INT ENA and RX ERR INT ENA

DG44
Intellectual 330 points

Hi,

I am using the SCI RX FIFO interrupt (SCIFFRX.bit.RXFFIENA = 1 and SCICTL2.bit.RXBKINTENA =1), with a 4 level FIFO.

It is working fine, but it is not detecting any RX errors even if I enable SCICTL1.bit.RXERRINTENA=1.

Can someone explain the RX interrupt logic and tell me what I need to do to have an interrupt associated with the RX errors ?

Thank you very much

  • 0
    Intellectual 300 points

    For the interrupt logic description, you can read page 861 of the document SPRUH18, and the interrupt block diagram is on page 863.

    IMO, to look or verify of whether you get an error interrupt, you must disable the RXRDY/BRKDT interrupt (SCICTL2, bit 1).  Whenever an error interrupt asserts, you can read the SCIRXST for an error flag, and then you must clear the flag by SW RESET bit.  Otherwise, you are not going to know what would cause the error when the next error interrupt happens.

    Hope that helps.

  • 0 in reply to Minhtuan Vo
    Intellectual 330 points

    Hi Minhtuan,

    The picture on page 863 answered all my questions. Sorry that I posted my question before look deep inside the manual.

    Thank you very much,

    Denise