TMS320F280025C: CLB configuration issues

A litle break, more reading...I had thought that the GIOP's would be configured by SYSCONFIG, because when I did that, I got a "resource conflict". Then, even though it looks like CLB INPUTXBAR is pointing to the correct GPIO pin, one must use the INPUTXBAR. 

After those things, my GPIO level is being passed through the CLB.

Howver, if you already know the answer to...

Ultimatley, what I want to do is have CMPSS2 come in to the CLB, trigger a 25uS timer that when the time is up, it send s sync pulse to PWM 4 to short cycle the period register while it is doing a cycle by cycle current limit. But one thing at a time...

Please do share, I think I have figured it out, but perhaps there is an easier way...

Hi David,

Glad you are looking into using the CLB, it really opens up a lot of potential for systems. A couple things to note:

To route a GPIO, you can use either a single CLB_INPUTXBAR or a combination of INPUTXBAR and CLB XBAR. There is no need to use all three if routing a single GPIO. I would say say to use CLB_INPUTXBAR so that you have leftover INPUTXBARs in case you need to route GPIOs to other peripherals. In your example, the CLB input should be configured to CLBINPUTXBAR INPUT5 on the local input mux.

(Note: INPUTXBAR5 is not the same as CLB_INPUTXBAR5, I see where the confusion might arise)

For the OUTPUTXBAR, same thing, I would say to use CLB_OUTPUTXBAR, the dedicated CLB outputs. This gives the benefit of letting you use any of the outputs of the CLB to output to a GPIO, instead of just OUT4 and OUT5.

For your system, here is the approach I would take to configuring the CLB:

Configure the CLBXBAR to grab the CMPSS signal in question, assign it to a desired AUXSIG signal.

In the CLB input, configure the CLB input to come from the AUXSIG on the global signal mux. I believe CMPSS is a single one shot trigger signal? If so, then configure rising edge detect filtering as an addition.

To implement the counter counting after the trigger, you can use the FSM to implement a two-state machine, (one state with counter stopped and another state with counter running) and the state transition being triggered by the CMPSS input. The state transition that brings output low can be when counter

Configure the counter "enable" signal to count up from the FSM output, and the reset/match1 value should be configured to a value corresponding to 25us (CLB is clocked at 100 MHz). 

Then OUTLUT can be configured to when this counter reaches the match 1 value. The state transition that brings FSM output low can be when counter reaches the match 1 value, too.

I also recommend looking at the CLB module and lab in C2000 Academy (https://dev.ti.com/tirex/global?id=c2000Academy). It is pretty helpful and the lab provides step-by-step instructions on a simple CLB implementation. I wrote this so please reach out if you have further suggestions on improving either module (there is also another Academy update coming out soon which adds more topics into the CLB module)

Regards,

Peter