Other Parts Discussed in Thread: SYSCONFIG
Here is a bit of code that the SysConfig came up with.
I have the PWM doing a Cycle by cycle limit using CMPSS2. that all works swimingly.
I have the Trip 5 signal going in to the CLB. That uses the State and counter to generate a pulse 10 micro seconds after the CMPSS2 signal comes in. That pulse gets routed to trip8 which gets routed to PWM3 Digital compare module. From what I see, the settings should allow trip 8 to generate a "sync" signal that will reset the tiem base counter.
It does not. I can not figure out why. I've tried using both EVTA1 and EVTB1 as the source. Niether do what I want...
Ideas?
EPWM_setClockPrescaler(EPWM3_DinA_BASE, EPWM_CLOCK_DIVIDER_2, EPWM_HSCLOCK_DIVIDER_1);
EPWM_setTimeBasePeriod(EPWM3_DinA_BASE, 2500);
EPWM_setTimeBaseCounter(EPWM3_DinA_BASE, 0);
EPWM_setTimeBaseCounterMode(EPWM3_DinA_BASE, EPWM_COUNTER_MODE_UP);
EPWM_disablePhaseShiftLoad(EPWM3_DinA_BASE);
EPWM_setPhaseShift(EPWM3_DinA_BASE, 0);
EPWM_setSyncInPulseSource(EPWM3_DinA_BASE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM3);
EPWM_enableSyncOutPulseSource(EPWM3_DinA_BASE, EPWM_SYNC_OUT_PULSE_ON_DCA_EVT1_SYNC);
EPWM_forceSyncPulse(EPWM3_DinA_BASE);
EPWM_setCounterCompareValue(EPWM3_DinA_BASE, EPWM_COUNTER_COMPARE_A, 0);
EPWM_setCounterCompareShadowLoadMode(EPWM3_DinA_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);
EPWM_setCounterCompareValue(EPWM3_DinA_BASE, EPWM_COUNTER_COMPARE_B, 0);
EPWM_setCounterCompareShadowLoadMode(EPWM3_DinA_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);
EPWM_disableCounterCompareShadowLoadMode(EPWM3_DinA_BASE, EPWM_COUNTER_COMPARE_C);
EPWM_disableCounterCompareShadowLoadMode(EPWM3_DinA_BASE, EPWM_COUNTER_COMPARE_D);
EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);
EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);
EPWM_setActionQualifierT1TriggerSource(EPWM3_DinA_BASE, EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1);
EPWM_setActionQualifierT2TriggerSource(EPWM3_DinA_BASE, EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1);
EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);
EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);
EPWM_setTripZoneAction(EPWM3_DinA_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW);
EPWM_setTripZoneAction(EPWM3_DinA_BASE, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW);
EPWM_setTripZoneAction(EPWM3_DinA_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT1, EPWM_TZ_ACTION_DISABLE);
EPWM_setTripZoneAction(EPWM3_DinA_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_DISABLE);
EPWM_setTripZoneAction(EPWM3_DinA_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT1, EPWM_TZ_ACTION_DISABLE);
EPWM_setTripZoneAction(EPWM3_DinA_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT2, EPWM_TZ_ACTION_DISABLE);
EPWM_enableTripZoneSignals(EPWM3_DinA_BASE, EPWM_TZ_SIGNAL_DCAEVT2);
EPWM_selectDigitalCompareTripInput(EPWM3_DinA_BASE, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCAH);
EPWM_selectDigitalCompareTripInput(EPWM3_DinA_BASE, EPWM_DC_TRIP_TRIPIN7, EPWM_DC_TYPE_DCAL);
EPWM_setTripZoneDigitalCompareEventCondition(EPWM3_DinA_BASE, EPWM_TZ_DC_OUTPUT_A1, EPWM_TZ_EVENT_DCXL_HIGH);
EPWM_setTripZoneDigitalCompareEventCondition(EPWM3_DinA_BASE, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXH_HIGH);
EPWM_enableDigitalCompareSyncEvent(EPWM3_DinA_BASE, EPWM_DC_MODULE_A);
EPWM_selectDigitalCompareTripInput(EPWM3_DinA_BASE, EPWM_DC_TRIP_TRIPIN8, EPWM_DC_TYPE_DCBH);
EPWM_setDigitalCompareEventSyncMode(EPWM3_DinA_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_INPUT_NOT_SYNCED);
EPWM_selectDigitalCompareCBCLatchClearEvent(EPWM3_DinA_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_CBC_LATCH_CLR_ON_CNTR_PERIOD);
EPWM_setDigitalCompareEventSyncMode(EPWM3_DinA_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_INPUT_NOT_SYNCED);
EPWM_setDigitalCompareFilterInput(EPWM3_DinA_BASE, EPWM_DC_WINDOW_SOURCE_DCBEVT1);
EPWM_enableDigitalCompareBlankingWindow(EPWM3_DinA_BASE);
EPWM_setDigitalCompareBlankingEvent(EPWM3_DinA_BASE, EPWM_DC_WINDOW_START_TBCTR_ZERO);
EPWM_enableADCTrigger(EPWM3_DinA_BASE, EPWM_SOC_A);
EPWM_setADCTriggerSource(EPWM3_DinA_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_ZERO);
