TMS320F28377D: Various arbitrations and interferences during memory/peripheral access

Hello Dmitry,

I will do some research and get back to you, there are some things I'm going to confirm.

Best regards,

Omer Amir

Hello Omer,

looking forward to hearing from you and thank you in advance.

And I want to correct one of my last questions, number 7: CAN cannot be accessed by DMA acc. to TRM, so question is wrong.
But let's reformulate it for SPI-A and SPI-B, which are allocated to different subsystems, for example.

Dmitry,

Dmitry Tuykov said:

2. I cannot find the arbitration scheme for 'CLA Message RAM' wihtin the TRM. Is it the same as Local Shared RAM?

Correct

Dmitry Tuykov said:

3. What is the arbitration scheme for 'CPU Message RAM'? Round-robin, the same as for Global Shared RAM?

Correct

Dmitry Tuykov said:

4. What is the arbitration scheme for uPP Configuration and RAM access between CPU1 and CPU1.CLA?

We need to look into this more, I would assume it follows the same as the global shared memories, but I need to check.  Will likely need until next week for same reasons as below

Dmitry Tuykov said:

5. Chapter 25.5.2 tells about 'high performance master arbitration block exists within the MCU to provide prioritized requests from the different sources to the EMIF', but what is the arbitration for EMIF1 (between CPUx and CPUx.DMA) and EMIF2 (between CPUx and CPUx.CLA)?

I need to get additional clarification here as well.  I don't want to speculate, and will need another colleague to reply.  He is currently out of the office returning next week.

Dmitry Tuykov said:

6. Some information within the chapter 5.6 is misleading.
In particular it says: "All instances of the same peripheral type conflict with each other. For instance, CAN-A and CAN-B conflict, as do the GS0 and GS2 RAMs.".
Could you please clarify GS0 and GS2 from this sentence? Will there be an arbitration in case of GS0 is accessing by CPUx and GS2 is accessing by CPUx.DMA, for example? Which arbitration scheme is applicable in this case, round-robin?
Is the same applicable for LSx and LSy for CPU and CLA access?

I need to follow up internally here, as I don't think this "bus sharing" applies to RAMs, i.e. GS0 and GS1 use shouldn't conflict with one another.  For the peripherals this is the correct behavior as there is a shared bus

Dmitry Tuykov said:

7. Let me please extend the previous question and the quote from it. What would happen if CAN-A is allocated to CPU1 subsystem and CAN-B is allocated to the CPU2 subsystem and concurrent access is done by CPU1 and CPU2 or CPU1 and CPU2.DMA or CPU1.DMA and CPU2.DMA? How arbitration is done if a periphery shared between differenc subsystems.

Will treat this as a peripheral that is accessible to all as you mentioned in your follow up post.  The fixed priority that you mention in you #8 applies here. So CLA/DMA write will have highest priority and so on.  Basically we can treat all peripherals of the same type as one unified memory range in terms of arbitration.

Dmitry Tuykov said:

8. Chapter 5.6 defines the following priorities for the arbitration:
• The fixed priority scheme for the peripheral frames is:
– CLA/DMA Write
– CLA/DMA Read
– CPU Write
– CPU Read
But it is not defined what has a higher priority. I suppose the 'CLA/DAM Write', please correct me if I'm wrong.

Yes, this should be a numbered list in the order shown in the TRM.

Will get back to you next week with the ones I have mentioned.

Best,

Matthew

Hello Matthew,

thank you very much for your prompt reply.
If you do not mind, I would clarify my question #7, to get the completely clear picture.

You mentioned that 'Basically we can treat all peripherals of the same type as one unified memory range in terms of arbitration'.
Let's suppose that SPI-A is allocated to CPU1 subsystem and SPI-B to CPU2 subsystem, second master is DMA for both subsystems. And we have concurrent access from both subsystems in any combination of masters. Which arbitration will take place here? If it is treated as a memory, I would expect round-robin. But it is a bit in a contradiction with the fixed priority from the chapter 5.6. If it a fixed priority, which subsystem has a higher prio? Or is it a mix? If yes, what kind of a mix?

Also I noticed one more suspicious thing in the chapter 5.6: 'Conflict Example: The CLA is accessing DAC-A while the DMA is simultaneously accessing DAC-B.'.
How is it possible if second master could be either CLA or DMA? Or is it about CPUx.CLA and CPUy.DMA from different subsystems (formally like in my question above)?

And I'm looking forward to hearing from you regarding two other open questions.

Thank you once again and have a nice day,
Dmitry

Dmitry,

I will add this to the list to check and get back.  Agreed that we need to be more specific here.

For your second point, I agree this must be from different subsystems, since peripherals can only be assigned to CLA or DMA but not both.

Best,

Matthew

Hello Matthew,

I found another interesting topic regarding arbitration but for another MCU: TMS320F28388D: Bus Interconnect scheme on Peripheral Bridge - C2000 microcontrollers forum - C2000︎ microcontrollers - TI E2E support forums

After reading it I even more confused about the arbitration of the peripherals of the same type in case of the allocation to different subsystems. There is a contradiction somewhere.

Best regards,
Dmitry

Dmitry,

Agree, I will follow up with Vivek on this and try to get a complete answer for you.  Thanks for referencing that other post as well.

Best,

Matthew

Hello Matthew,

have you had a chance to clarify my questions above?

Thanks for you help in advance,
Dmitry

Dmitry Tuykov said:

4. What is the arbitration scheme for uPP Configuration and RAM access between CPU1 and CPU1.CLA?

This will follow the same scheme as peripheral arbitration with fixed priority:

1. CLA/DMA Write
2. CLA/DMA Read
3. CPU Write
4. CPU Read

Dmitry Tuykov said:

5. Chapter 25.5.2 tells about 'high performance master arbitration block exists within the MCU to provide prioritized requests from the different sources to the EMIF', but what is the arbitration for EMIF1 (between CPUx and CPUx.DMA) and EMIF2 (between CPUx and CPUx.CLA)?

There is a semaphore that defines ownership.  Write can only come from the owner, reads will be handled the same as the global shared RAM scheme, we will add a note/link from the DMA chapter back to the memory arbitration chapter to clear this up.

Dmitry Tuykov said:

6. Some information within the chapter 5.6 is misleading.
In particular it says: "All instances of the same peripheral type conflict with each other. For instance, CAN-A and CAN-B conflict, as do the GS0 and GS2 RAMs.".
Could you please clarify GS0 and GS2 from this sentence? Will there be an arbitration in case of GS0 is accessing by CPUx and GS2 is accessing by CPUx.DMA, for example? Which arbitration scheme is applicable in this case, round-robin?
Is the same applicable for LSx and LSy for CPU and CLA access?

For peripherals in the same CPU ownership domain what we mentioned/TRM still holds.  However, if the peripherals, even if in the same group, are assigned different CPU domains then there are separate busses for that.  So if CAN-A is owned by CPU1 and CAN-B is owned by CPU2 then those access could happen concurrently.  Within a CPU domain the fixed peripheral arbitration will apply from above.

The comment on GS0/GS2 is wrong(as I assumed) and we will remove that in the next update of this document.  RAM has full parallel bussing per RAM block.

Best,

Matthew

Hello Matthew,

almost clear. I have last couple of questions to clarify and we can close the topic:

MatthewPate said:

Dmitry Tuykov said:

4. What is the arbitration scheme for uPP Configuration and RAM access between CPU1 and CPU1.CLA?

This will follow the same scheme as peripheral arbitration with fixed priority:

1. CLA/DMA Write
2. CLA/DMA Read
3. CPU Write
4. CPU Read

Is it applicable to uPP RAM as well? So if CLA is continuously writing/reading to/from uPP RAM, CPU has no chance to get access, has it?

MatthewPate said:

Dmitry Tuykov said:

5. Chapter 25.5.2 tells about 'high performance master arbitration block exists within the MCU to provide prioritized requests from the different sources to the EMIF', but what is the arbitration for EMIF1 (between CPUx and CPUx.DMA) and EMIF2 (between CPUx and CPUx.CLA)?

There is a semaphore that defines ownership.  Write can only come from the owner, reads will be handled the same as the global shared RAM scheme, we will add a note/link from the DMA chapter back to the memory arbitration chapter to clear this up.

But the owner is a subsystem (depends on MSEL_EMIFx), if I understand it correctly.
Within the subsystem there are two masters. Cannot they both concurrently access EMIF with write operation? Is it also arbitrated with round robin or?

Question 6 is clear now, closed


And one additional question, if you do not mind.
Some RAMs (e.g. Global Shared) have write protection for CPU or DMA. If this protection is enabled and write happens, will it lead to an arbitration at the bus as well or not?

Thank you in advance,

Dmitry

Hi Dmitry,

Dmitry Tuykov said:

Is it applicable to uPP RAM as well? So if CLA is continuously writing/reading to/from uPP RAM, CPU has no chance to get access, has it?

Yes, it's applicable to RAM as well. Yes, if CLA is continuously accessing it then CPU will not get chance to access it but the way it'll work is CLA (or CPU) need to read data from some where (or process it) and then access the uPP RAM so there will be idle cycles where CPU will get opportunity to service. In normal condition this should never happen.

Also please note that we are not supporting uPP on our future roadmap device hence we do not recommend using this IP unless it's absolute necessary.

Dmitry Tuykov said:

But the owner is a subsystem (depends on MSEL_EMIFx), if I understand it correctly.
Within the subsystem there are two masters. Cannot they both concurrently access EMIF with write operation? Is it also arbitrated with round robin or?

No, write access is only allowed for the initiators from subsystem which has ownership of EMIF. 

Dmitry Tuykov said:

Some RAMs (e.g. Global Shared) have write protection for CPU or DMA. If this protection is enabled and write happens, will it lead to an arbitration at the bus as well or not?

Good question. I think in this case the access does not go to arbitration block but I'll double check this and confirm.

Regards,

Vivek Singh

Hi Vivek,

Vivek Singh said:

Dmitry Tuykov said:

But the owner is a subsystem (depends on MSEL_EMIFx), if I understand it correctly.
Within the subsystem there are two masters. Cannot they both concurrently access EMIF with write operation? Is it also arbitrated with round robin or?

No, write access is only allowed for the initiators from subsystem which has ownership of EMIF. 

hmmm...not completely clear, could you please clarify, maybe with some simple examples.
Based on the table 9-10 from the TMS320F28377D datasheet I would suppose that:
- EMIF1 can be accessed from CPUx and CPUx.DMA concurrently, incl. write access (where 'x' depends on MSEL_EMIF1)
- EMIF2 can be accessed from CPU1 and CPU1.CLA concurrently, incl. write access
So I would expect some arbitration between these masters from the subsystem which has ownership of EMIF.
Also the following information is defined in SPUHM8I:
"If a request is submitted from two or more sources simultaneously, the crossbar switch will forward the
highest priority request to the EMIF first. Upon completion of a request, the master arbitration block again
evaluates the pending requests and forwards the highest priority pending request to the EMIF."
But what is the highest - not clear.

And looking forward to hearing from you regarding arbitration in case of protection violation for RAM.

Thank you and have a nice day,
Dmitry

Dmitry Tuykov said:

Based on the table 9-10 from the TMS320F28377D datasheet I would suppose that:
- EMIF1 can be accessed from CPUx and CPUx.DMA concurrently, incl. write access (where 'x' depends on MSEL_EMIF1)
- EMIF2 can be accessed from CPU1 and CPU1.CLA concurrently, incl. write access
So I would expect some arbitration between these masters from the subsystem which has ownership of EMIF.

This is correct and as Matt mentioned earlier, arbitration scheme is same as one for Global RAMs.

Dmitry Tuykov said:

"If a request is submitted from two or more sources simultaneously, the crossbar switch will forward the
highest priority request to the EMIF first. Upon completion of a request, the master arbitration block again
evaluates the pending requests and forwards the highest priority pending request to the EMIF."

As mentioned, the arbitration scheme is same as of Global RAM so please refer section "3.11.1.6 Access Arbitration" for the same.

Regards,

Vivek Singh

Hi Vivek,

it is clear now regarding the EMIF, probably I lost the thread. So grabbing by a subsystem + round robin within a subsystem.
Hope for your support with RAM protection + arbitration and this long topic could be closed.

Have a nice weekend,
Dmitry

Yes, will get back to you early next week.

Regards,

Vivek Singh

Hello Vivek,

good to know it, this case there is less interferences possible.

Thank you for this and all your previous answers once again, topic could be closed.

Best regards,
Dmitry