• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 82 subscribers
  • Views 258 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28388D: AES-3 Bit Count Output Using CLB Counters

Ben Williams
Prodigy 10 points

Part Number: TMS320F28388D

Hello.

I'm currently in the progress of removing an FPGA from a latency AES-3 transmitter board and moving over to a microcontroller solution using the TMS320F28388D.

At the moment the microcontroller is a good match and hits all the requirements. But there is one element that I require feedback on.

For my application I require an 32 bit counter that can shifted out on a enable signal (LRCLK) and shifted out on a clocking out signal(SCLK). Both these signals are connected to the GPIO from the AES-3 waveform generator. Below I have attached a image to show what I'm after. The counter will be updated every 10Hz by the main code running in the first core.

I'm looking at using namely the 'CLB' (It's my first time using this feature) To ensure that they are in phase with minimal delay between signals, just like what you would get with a FPGA solution.

But would love some feedback if this is possible using the 'CLB' block. From reading the user guide it does look like that a counter set in 'serializer mode' can be used to shift out the data but wasn't sure if the operation can be clocked against my SCLK signal and enabled via the LRCLK signal.

I'm quite keen to get the 'CLB' block developed as it will be a great device to use instead of a FPGA in certain applications. 

Thank you for your time.

  • 0
    TI__Mastermind 22351 points

    Hi Ben, 

    Thanks for providing a detailed overview on your system, it helps to assess if the CLB can do what you're wanting. Below is the description of the serializer function from the TRM

    The enable functionality you are looking for would work if you route the LRCLK signal to the MODE_0 input of the counter, and the shifting can be clocked to the SCLK by assigning that signal to either of the MATCH inputs of the counter. Let me know if you have any other questions or need more explanation. We have a few other resources for CLB development, most notably a learning module and lab exercise in our C2000 Academy (https://dev.ti.com/tirex/global?id=c2000Academy)

    Regards,

    Peter

  • 0 in reply to Peter Luong
    Prodigy 10 points

    Hello, Peter.

    Thank you for your reply, its certainly helps and gives me confidence that the CLB can be used for my application. 

    Also thank you for the link. I'll spend some time looking over this.

    Just a quick follow up question when the counter is set to 'serializer mode', does it lose it's counter function? Or would I have to add another counter and connect it's output to the 'Event' pin input to clock in the counter.

    Ideally I would like to leave all the counters and shifting in the 'CLB' block and update the count when needed from the main loop in Core 1.

    Kind regards

    Ben W

  • 0 in reply to Ben Williams
    TI__Mastermind 22351 points

    Hi Ben,

    Can you clarify what you mean by lose its counter function? The inputs of the counter are repurposed in serializer mode so you wouldn't be able to use the same count up, count down, etc. functions that the typical counter would have. The counter would solely be used as shift register for you to load in and tap out bits. Like you mentioned, another counter (not in serializer mode) would have to be used

    Regards,

    Peter