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TMS320F28384D: The maximum error rate of SCI communication

Luke Chen
Expert 5090 points

Part Number: TMS320F28384D

Hi champs,

Speaking of SCI communication, the processor determines the bit value by making three samples in the middle of the bits(fourth, fifth and sixth SCICLK periods).

If there is one host with inaccurate baud rate, what's the maximum error rate tolerance so that C28x can still receive correct data frame?

Regards,

Luke

  • 0
    TI__Mastermind 19795 points

    Hi Luke,

    Thanks for your question. Due to the fact that a noisy system or clock/baud jitter from noise can make even a "perfect baud rate" have a failure, there's not really an easy answer to this. But if you're assuming baud rates do not have any jitter, then:

    Assuming max bits between "start" and "sync" bits of 12 bits, and both baud rates perfectly aligned at the start of timing:

    * For guaranteed failure >4.1% total error tolerance between the baud rates will guarantee an eventual error

    * Note that this error % includes all timing errors, including but not limited to: oscillator precision error, jitter, noise, baud inaccuracy, baud granularity (ability to set a baud rate), difference in effective baud rates.

    I would also HIGHLY RECOMMEND ensuring the C28x device is receiving data with 2 stop-bits in between bytes, when using any SCI interrupts. Meaning the other device that is sending to C28x should send with 2 stop-bits. This is because the processing time between stop bit and ISR start is ((7*BAUD_CLK_PERIOD)/8 + 3*SYSCLK_PERIOD. So approximately 7/8 of a baud period before ISR begins processing. 1 stop-bit would allow less than 1/8th of a baud period to process the ISR.

    Regards,

    Vince

  • 0 in reply to Vince
    TI__Expert 5090 points

    Vince,

    The error rate will be accumulated if receive more bits. For example, if bit error rate is 1%, then the error rate will be 10% if when receive the tenth bit.

    However, base on the SCI bit sampling method(fourth, fifth and sixth SCICLK periods), I am thinking the SCI has 25% error rate tolerance(the seventh and eighth SCICLK periods), means that if the accumulated bit error rate is less than 25%, then SCI should work well without problem.

    How do you think?

    Regards,

    Luke 

  • +1 in reply to Luke Chen
    TI__Mastermind 19795 points

    Hi Luke,

    Luke Chen said:
    However, base on the SCI bit sampling method(fourth, fifth and sixth SCICLK periods), I am thinking the SCI has 25% error rate tolerance(the seventh and eighth SCICLK periods), means that if the accumulated bit error rate is less than 25%, then SCI should work well without problem.

    This understanding you provided above, if I am reading it correctly, is incorrect. It will not be an accumulated 25% error rate.

    Although accumulated error will play a factor, the total accumulated error must lead to a shift within one byte (12 bits) of less than 4.1%.

    Here is a diagram explaining the two extreme error conditions. “SLOW CLOCK” and “FAST CLOCK” are from receiver point of view compared to the data coming in.

     

    Assuming a byte has 12-bits total, then the below table shows at what point the strobes will register an incorrect bit:

    TOTAL BITS PER FRAME

    12

    STOP BIT 5TH STROBE

    93    (SCI CLOCKS FROM FRAME START)

    IDEAL STOP BIT FINAL EDGE

    97    (SCI CLOCKS FROM FRAME START)

    IDEAL STOP BIT LEADING EDGE

    89    (SCI CLOCKS FROM FRAME START)

    SLOW CLOCK MAX ERROR PERCENTAGE

    4.12  (%) <-- this is the lowest percent, and so is the limit we must use.

    SLOW CLOCK MAX TIE

    4.0   (Time Interval Error in SCI CLOCKS, interval=start_bit leading to stop_bit final edge)

    FAST CLOCK MAX ERROR PERCENTAGE

    4.49  (%)

    FAST CLOCK MAX TIE

    4.0   (Time Interval Error in SCI CLOCKS, interval=start_bit leading to stop_bit leading edge)

    This applies regardless of how many bytes are sent. The adjustment period happens each byte. So accumulated error must be enough within 1 byte to cause an error. This happens with baud rate of 4.1% or more.

    Regards,

    Vince