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Original question:

TMS320F280039C: Accurate timing from triggering to Sample and Hold

TMS320F280039C: discharging the internal ADC S+H capacitor ?

Bernhard Kainz
Prodigy 90 points
Part Number: TMS320F280039C


Hi everyone,

I have a  question regarding the sample and hold cap of the ADC. In the document (SPRACT6 – OCTOBER 2020 ADC Input Circuit Evaluation for C2000 MCUs) @ page 3 I found the following information:

Some ADC
architectural implementations will have a starting S+H voltage close to the previously sampled voltage while
other architectures will usually start the acquisition phase with a discharged S+H capacitor.

My question:

What architecture has now the TMS320F280039C controller? Is the S+H capacitor discharged before it starts a new AD conversion at a multiple channel sequence? Or does the S+H capacitor remains charged closed to the previous sampled channel?

Is there a software configuration available to select, if the S+H capacitor is discharged before the next sampling starts?

Thanks

Bernhard

http://www.ti.com/lit/zip/spract6

  • +1
    TI__Mastermind 38990 points

    Hi Bernard,

    F280039C would still have this issue where inadequate settling would cause the channel to to be pulled towards the previously converted voltage.  Ensuring enough SH time, as discussed in section 16.13.2 (Choosing an Acquisition Window Duration) of the TRM should minimize this effect.  Another alternative is to convert VREFLO prior to sampling the actual channel/signal of interest.  This way, the sampling capacitor can be allowed to discharge close to VREFLO/GND level.  In F280039C, choosing channel 13 for any of the ADCs will internally connect the ADC input mux to VREFLO (refer to Table 6-9 on the datasheet).

    Regards,

    Joseph

  • 0 in reply to Joseph Casuga
    Prodigy 90 points

    Hi Joseph,

    many thanks for your clarifications and help. 

    BR

    Bernhard