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TMS320F280039C: The CLB function generates orthogonal signals(AB)

qing yuan sun
Prodigy 100 points
Part Number: TMS320F280039C
Other Parts Discussed in Thread: C2000WARE, SYSCONFIG

hello!

CCS Version: 11.1.0.00011 

C:\ti\c2000\C2000Ware_4_01_00_00\driverlib\f28003x\examples\clb----clb_ex3_auxiliary_pwm

I changed this example,

I want to change the period value of the AB signal by changing the value of match1,But when I give R1 a small value by changing CLB_setHLCRegisters(myTILE1_BASE, 0, 1000, 0, 0), the AB signal cannot be generated,A larger value for R1 produces the AB signal

I don't know why,hope to get help

  • 0
    TI__Mastermind 19411 points

    Hi Qing,

    Thanks for reaching out. Let me look into this issue, this is the first I'm hearing about this. What values have you tried passing into the registers?

    Regards,

    Peter

  • 0 in reply to Peter Luong1
    Prodigy 100 points

    Hi Peter,

    My main goal is to change the value of match1 so as to change the AB signal frequency,I put CLB_setHLCRegisters into clb1ISR, and for R1 values below 500, the CLB module will not send waves,

    Regards,

    Qing

  • 0 in reply to Peter Luong1
    Prodigy 100 points

    HI Peter

    This problem comes up easily,You can import ex3 and make two changes,

    As shown in figure

    You can debug and give periodValue

    This problem occurs if you give a value less than 1000.

    To summarize, the main question point is how can I write to match1 quickly and make it work. If we put CLB_setHLCRegisters in while(1), the same thing happens

  • 0 in reply to qing yuan sun
    TI__Mastermind 19411 points

    Hi Qing,

    Thanks for reaching out. Let me assign this over to my colleague Luke, he has actually been debugging the same issue on this example. You are correct when saying that the issue is that you want to pass the value from the ISR function to the match1 condition as quickly as possible, which involves reducing the latency of the ISR function. Since there is no way to directly write to the match1 condition, the way to do this would involve using the HWREG calls that each DriverLib function uses (Ctrl+clicking into the function). If you know for sure that the values being passed into the calls are valid, then you can reduce unnecessary clock cycles that are used for error-checking. Let me know if you have any questions on this, but I will allow my colleague Luke to share more of his findings.

    Regards,

    Peter

  • 0 in reply to Peter Luong1
    Prodigy 100 points

    HI peter

    If I want to make a quick change to match1,What should I do?

    In other words,I follow the following method to realize whether the AB signal is correct?

    Because my goal is to achieve variable frequency AB signals

    Regards,

    Qing

  • 0 in reply to Peter Luong1
    Prodigy 100 points

    HI Peter

    I'm trying to understand you,You mean the same way as below?

    HWREG(myTILE1_BASE + CLB_DATAEXCH + CLB_O_PULL(0)) = period;
    HWREG(myTILE1_BASE + CLB_DATAEXCH + CLB_O_PULL(1)) = duty;

    It is written to R0, R1 of HLC in this way, and then to match1 in response to EVENT?

  • 0 in reply to qing yuan sun
    TI__Mastermind 28220 points

    Hi Qing,

    when event0 is triggered by match1, the HLC executes a small program that moves the contents of R0 into counter0_match2, and then triggers the interrupt. You can see this program in the "Other Dependencies" inside of the HLC menu in SysConfig.

    In terms of what registers to write to using HWREG, I would suggest opening the declaration of CLB_setHLCRegisters(myTILE1_BASE, dutyValue, 0, 0, 0); until you only have the instructions you need. Eventually you will only need these 5 instructions to write to one of the HLC's registers(located in the CLB_writeInterface function in clb.h:

    EALLOW;
    HWREG(base + CLB_LOGICCTL + CLB_O_LOAD_ADDR) = address;
    HWREG(base + CLB_LOGICCTL + CLB_O_LOAD_DATA) = value;
    HWREG(base + CLB_LOGICCTL + CLB_O_LOAD_EN) |= CLB_LOAD_EN_LOAD_EN;
    EDIS;

    For some background, we've uncovered an issue in this example where it does not function properly if the ISR takes longer to execute than the CLB's counter0 period. A counter period of 300 works on some devices such F2837x but not on F28003x. This is due to the varying ratio between the system clock and CLB clock when comparing devices, and the varying time it takes for certain driverlib functions to execute on different devices. If you want a shorter period you will have to remove the unnecessary instructions, and observe the GPIO0 signal to determine whether your ISR is executing before the end of the counter period.

    Thank you,

    Luke

  • 0 in reply to Luke Jones
    Prodigy 100 points

    HI Luke

    Thank you. I see the reason for the problem,but，If I want to make a quick change to match1,What should I do?

    Qing

  • 0 in reply to qing yuan sun
    TI__Mastermind 28220 points

    Hi Qing,

    I am not sure what you mean by a "quick change". If you are asking if there's a way to directly write to match1 during runtime, this is not possible using SysConfig, but you can try using the CLB_writeInterface(base, CLB_ADDR_COUNTER_0_MATCH1, match1) function found in clb.c.

    Thank you,

    Luke

  • 0 in reply to Luke Jones
    Prodigy 100 points

    HI Luke

    Ok, thank you, I'll try

    Qing