TMS320F2812: the output of clock abnormal until after repeatedly reset

Yale,

Do you mean that with PLLCR = 0x8 there is the same issue with clock out = 30MHz, or that this config gets a 120MHz clock correctly?

Is customer using the TI function for changing the PLL in sysctrl.c

EALLOW;
      SysCtrlRegs.PLLCR.bit.DIV = val;
      EDIS;

   // Optional: Wait for PLL to lock.
   // During this time the CPU will switch to OSCCLK/2 until the PLL is
   // stable.  Once the PLL is stable the CPU will switch to the new PLL value.
   //
   // This switch time is 131072 CLKIN cycles as of Rev C silicon.
   //
   // Code is not required to sit and wait for the PLL to lock.
   // However, if the code does anything that is timing critical,
   // and requires the correct clock be locked, then it is best to
   // wait until this switching has completed.

   // If this function is run from waitstated memory, then the loop count can
   // be reduced as long as the minimum switch time is still met.

   // iVol is volatile so the compiler will not optimize this loop out
   //
   // The watchdog should be disabled before this loop, or fed within
   // the loop.

      DisableDog();

   // Wait lock cycles.
   // Note,  This loop is tuned to 0-waitstate RAM memory.  If this
   // function is run from wait-stated memory such as Flash or XINTF,
   // then the number of times through the loop can be reduced
   // accordingly.
      for(iVol= 0; iVol< ( (131072/2)/12 ); iVol++)

There is a needed wait time, and watchdog needs to be disabled during this time so it will not reset the device.

If customer is following the above, then perhaps there is an issue in customer's system going from 30MHz to 150MHz in one step.  This could be caused if the chip cannot meet its in-rush current demands when the above change takes place.  A potential soln would be to step the PLL in increments to gradually increase the current load until 150MHz is released.

If none of the above work, I would ask the customer to monitor the XRSn pin during the PLL change for any reset coming from the device.

Best,
Matthew

Yale,

Do you mean CCS/Debugger reset?  Is customer using the GEL command "set PLL Ratio" to set the clock or doing this through code execution?

Best,

Matthew

Hi Matthew,

We found the reason. The customer didn't connect the pull-up resistance on XPLLDIS pin.

Very appreciate about your help!

Thanks & Regards

Yale Li