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TMS320F28388D: IER

Part Number: TMS320F28388D


Hi team,

Here's an issue from the customer may need your help:

Why is IER cleared after the CPU saves its context on the stack? If cleared, the interrupt signal is disconnected from the CPU.

"Writes to IER and INTM are atomic operations", does this refer to the CPU automatically operate two bits? Manual does not seem to mention when IER will be set again.

When using this bit, the IER bit is normally set in initialization, right? If the IER bit is cleared after the save context, the user needs to add instructions to set it again. The customer did not change the IER status again when coding.

Could you help check this case? Thanks.

Best Regards,

Cherry

  • Hi Cherry,

    Thanks for your questions. Please see my answers to each in order below:

    Why is IER cleared after the CPU saves its context on the stack? If cleared, the interrupt signal is disconnected from the CPU.

    IER is cleared is to prevent further interrupts from triggering during the entry process and throughout the rest of the ISR. Essentially, this prevents spurious interrupts.

      

    "Writes to IER and INTM are atomic operations", does this refer to the CPU automatically operate two bits? Manual does not seem to mention when IER will be set again.

    Atomic operations here refer to the fact that these two write instructions cannot be interrupted.

      

    When using this bit, the IER bit is normally set in initialization, right? If the IER bit is cleared after the save context, the user needs to add instructions to set it again. The customer did not change the IER status again when coding.

    Please see row #13 below from the nesting interrupts page, there is an automatic context restore in the hardware that restores the IER automatically. No need for customer to do this in software.

    https://software-dl.ti.com/C2000/docs/c28x_interrupt_nesting/html/index.html

    Regards,

    Vince