This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28379D: Porting CLA code from RAM to FLASH

Part Number: TMS320F28379D

Hello,

I need CLA for my current project.

To get started, I ran the IIR2P2Z project from RAM. No major problems there (had to LOAD SYMBOLS from the Run menu).

Now I have copied the complete IIR2P2Z code into my - quite lightweight - project that runs from FLASH.

However, the IIR2P2Z function "void CLA_runTest(void)" does not finish. It is stuck at Task 8 with the blue debug arrow stopped at the first line. This is odd since there is no debug instruction in this CLA Task:

//Task 8 will initialize the variables used in Task 1

interrupt void Cla1Task8 ( void )
{
W2[0] = 1; W2[1] = 2;
W1[0] = 1; W1[1] = 2;

The corresponding bit in the MIRUN register is set to 1, which means that Task 8 is still running. The CLA peripheral clock is enabled.

void CLA_runTest(void)
{
int16_t i;
float fError[NUM_SAMPLES];

Cla1ForceTask8andWait();   <--------- STUCK HERE ---------------
WAITSTEP;

for(i=0; i < NUM_SAMPLES; i++)
{
xn = fAdcInput[i];

Cla1ForceTask1andWait();
WAITSTEP;

fBiquadOutput[i] = yn;

fError[i] = fabs(iir_expected[i]-fBiquadOutput[i]);

if(fError[i] < 0.01)
{
pass++;
}
else
{
fail++;
}

}

Is there something I am missing?

  • Can you conform that the CLA code is copied to LSRAM which is configured as CLA program memory?

    Regards,

    Veena

  • The issue was with the linker file.

    1) Now I use LS0 as the data memory location and LS4 as the program memory location for the CLA. No other code/data is located there anymore.

    //
    // Select LS4RAM to be the programming space for the CLA
    // First configure the CLA to be the master for LS5 and then
    // set the space to be a program block
    //
    MemCfgRegs.LSxMSEL.bit.MSEL_LS4 = 1;
    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS4 = 1;

    //
    // Next configure LS0RAM as data spaces for the CLA
    // First configure the CLA to be the master for LS0(1) and then
    // set the spaces to be code blocks
    //
    MemCfgRegs.LSxMSEL.bit.MSEL_LS0 = 1;
    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS0 = 0;

    2) Had to add this code to my linker file (found online).

    // The user must define CLA_C in the project linker settings if using the
    // CLA C compiler
    // Project Properties -> C2000 Linker -> Advanced Options -> Command File
    // Preprocessing -> --define
    #ifdef CLA_C
    // Define a size for the CLA scratchpad area that will be used
    // by the CLA compiler for local symbols and temps
    // Also force references to the special symbols that mark the
    // scratchpad are.
    CLA_SCRATCHPAD_SIZE = 0x100;
    --undef_sym=__cla_scratchpad_end
    --undef_sym=__cla_scratchpad_start
    #endif

    /* CLA specific sections */
    Cla1Prog : LOAD = FLASHD,
    RUN = RAMLS4,
    LOAD_START(_Cla1funcsLoadStart),
    LOAD_END(_Cla1funcsLoadEnd),
    RUN_START(_Cla1funcsRunStart),
    LOAD_SIZE(_Cla1funcsLoadSize),
    PAGE = 0, ALIGN(4)

    /* ClaData : > RAMLS0, PAGE=0, ALIGN=2*/
    CLADataLS0 : > RAMLS0, PAGE=1, ALIGN=2

    Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
    CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1

    #ifdef CLA_C
    /* CLA C compiler sections */
    //
    // Must be allocated to memory the CLA has write access to
    //
    CLAscratch :
    { *.obj(CLAscratch)
    . += CLA_SCRATCHPAD_SIZE;
    *.obj(CLAscratch_end) } > RAMLS0, PAGE = 1

    .scratchpad : > RAMLS0, PAGE = 1
    .bss_cla : > RAMLS0, PAGE = 1
    .const_cla : LOAD = FLASHB,
    RUN = RAMLS0,
    RUN_START(_Cla1ConstRunStart),
    LOAD_START(_Cla1ConstLoadStart),
    LOAD_SIZE(_Cla1ConstLoadSize),
    PAGE = 1
    #endif //CLA_C

    Could you please point me to a document that discusses the scratch pad? I searched through spruhm8h but could not find anything relevant.

    Thank you,

    Tomas

  • https://www.ti.com/lit/ug/spru513w/spru513w.pdf

    This should have details on scratchpad section

    Regards,

    Veena

  • Thank you.

    One more question - could you please point me to some literature that explains why it is not advisable to use the same memory block for both the CLA and CPU to both read & write - as shown below.  Would this result in incorrect behavior or just read/write delays should the CPU/CLA combo try to access the same memory block at the same time? 

    Memory Section

    CPU

    CLA

    CpuToCla1MsgRAM Read & Write Read only
    Cla1ToCpuMsgRAM Read only Read & Write
    Cla1DataRAM Read & Write Read & Write
  • You can configure an LSRAM as CLA data memory - Both CPU and CLA has read & write access to this memory.

    There is no restriction on using such shared memory. Since both cores have read write access, application need to take of avoiding conflicts such as both cores writing to the same address simultaneously

    Regards,

    Veena