TMS320F28379D: Serial Flash Programmer Core 2 error

Hi Zvi,

According to the Serial Flash Programming of C2000 MCU's  document, when loading the 2 kernel cores using CCS, are you making sure to use the correct build settings for both cores? Is one set to RAM and the other to Flash? The Verify Error indicates that the location has not been programmed (has data not expected), therefore it might be at another location.

Regards,

Charles

Hello Charles,

I am not loading using CCS, I am trying to load using serial flash bootloader and when it fails I am using UNIFLASH to burn the original out file for core 2.

Both cores set to Flash. There are no issues after burning with UNIFLASH.

We are using Matlab / Simulink for code generation and both of the cores are configured the same way. 

I also read flash memory with UNIFLAH  after bootloader failure and I can see that 8 bytes are not programmed starting with address 0x090002.

On the other hand when using UNIFLASH to burn out file those 8 bytes are not empty.

Maybe hex2000 not producing data for bootloader ?

Best regards.

Hi Zvi,

I see, Uniflash not CCS. Testing the f28379D now. For the 8 bytes that are missing at 0x090002, will check the hex2000 utility as well. Reporting back as soon as possible.

Zvi, could this be an alignment issue with hex2000 in the serial flash programmer?  Are your files ALIGN(8) for all the initialized sections that are mapped to flash in the linker command file for both kernel cores?

Thanks,

Charles

We are using:

Compiler version v18.12.2 LTS ( hex2000 also from this release )

C2000Ware version 2.00.00.02 - for Matlab / Simulink code generation and  serial_flash_bootloader.exe

Hope this info will help you.

Zvi,

Can you show an image of the error occurring or what the error code/message is that stops the hex2000? Is it possible to update the compiler version to the latest build? Currently on 22.6. Will look into this specific version of C2K.

Thanks,

Charles

Hello Charles,

1. I am using linker command file provided by Matlab and there is ALIGN(4) - I'll try with ALIGN(8)
2. Matlab 2019b is using this version of compiler but I'll try to use version 22.6

Great, 

Let me know what changes.

Hello Charles,

• ALIGN(8) - after compiling with this change and trying with serial bootloader the result was a different error:

ERROR Status: PROGRAM_ERROR

ERROR Address: 0x220026

• Compiler version 22.6 cannot be used because the program compiles OK and not running correctly

I don't understand why there is a different error after changing to ALIGN(8) and why the address is of EMIF1_CS2 which we don't have ?!

Zvi,

Success of command is a good, it means that the operation was successful. The error of PROGRAM_ERROR indicates that the application file has sections not mapped to flash memory. The error address is 0x220026, which is odd. Now that you are using ALIGN(8), can you try to look at your application linker cmd file to see if any section is mapped incorrectly? There is a memory map for the device as well that shows the range of memory available.

Thanks,

Charles

Hello Charles,

I think it is time to look together at the linker command file - because there is nothing in it to suggest that we mapped our memory incorrectly :

#include "MW_F2837xD_MemoryMap.h"
#ifdef CLA_BLOCK_INCLUDED
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are. 
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
#endif //CLA_BLOCK_INCLUDED
MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
   BEGIN           	: origin = 0x000000, length = 0x000002
   BEGIN_FLASH     	: origin = 0x080000, length = 0x000002
   #ifdef CLA_BLOCK_INCLUDED
        RAMLS_PROG      	: origin = 0x008000, length = 0x001800
        RAMLS_CLA_PROG      : origin = 0x00A800, length = 0x000800
   #else
        #if BOOT_FROM_FLASH
            RAMLS_PROG      	: origin = 0x008000, length = 0x002000
        #else
            RAMLS_PROG      	: origin = 0x008000, length = 0x003000
        #endif //BOOT_FROM_FLASH
   #endif //CLA_BLOCK_INCLUDED
   
   #ifdef CPU1       
        #if (CPU1_RAMGS_PROG_LENGTH > 0)
            RAMGS_PROG          : origin = CPU1_RAMGS_PROG_START, length = CPU1_RAMGS_PROG_LENGTH
        #endif //(CPU1_RAMGS_PROG_LENGTH > 0)
   #else
        #if (CPU2_RAMGS_PROG_LENGTH > 0)
            RAMGS_PROG          : origin = CPU2_RAMGS_PROG_START, length = CPU2_RAMGS_PROG_LENGTH
       #endif //(CPU2_RAMGS_PROG_LENGTH > 0)
   #endif //CPU1

   RESET           	: origin = 0x3FFFC0, length = 0x000002
   /* Flash sectors */
   #if defined(F28376D) || defined(F28374D)
        FLASHA_N           : origin = 0x080002, length = 0x01FFFE	/* on-chip Flash */ 
   #else
        FLASHA_N           : origin = 0x080002, length = 0x03FFFE	/* on-chip Flash */ 
   #endif //defined(F28376D) || defined(F28374D)

PAGE 1 :
   #ifdef CPU1
       BOOT_RSVD           : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
   #else
       BOOT_RSVD           : origin = 0x000002, length = 0x00007E     /* Part of M0, BOOT rom will use this for stack */
   #endif //CPU1

   #ifdef CPU1
       RAMM0M1           	: origin = 0x000122, length = 0x0006DE
   #else
       RAMM0M1           	: origin = 0x000080, length = 0x000780
   #endif //CPU1

   RAMD0D1           	: origin = 0x00B000, length = 0x001000

   #ifdef CLA_BLOCK_INCLUDED
        RAMLS_CLA_DATA      : origin = 0x009800, length = 0x001000
   #else
        #if BOOT_FROM_FLASH
            RAMLS_DATA          : origin = 0x00A000, length = 0x001000
        #endif //BOOT_FROM_FLASH
   #endif //CLA_BLOCK_INCLUDED

#ifdef CPU1       
        RAMGS_DATA       : origin = CPU1_RAMGS_DATA_START, length = CPU1_RAMGS_DATA_LENGTH
#else
        RAMGS_DATA       : origin = CPU2_RAMGS_DATA_START, length = CPU2_RAMGS_DATA_LENGTH
#endif //CPU1

   RAMGS_IPCBuffCPU1   : origin = RAMGS_IPC_CPU1_START, length = RAMGS_IPC_CPU1_LENGTH
   RAMGS_IPCBuffCPU2   : origin = RAMGS_IPC_CPU2_START, length = RAMGS_IPC_CPU2_LENGTH 

   CLA1_MSGRAMLOW      : origin = 0x001480, length = 0x000080
   CLA1_MSGRAMHIGH     : origin = 0x001500, length = 0x000080

   CPU2TOCPU1RAM       : origin = 0x03F800, length = 0x000400
   CPU1TOCPU2RAM       : origin = 0x03FC00, length = 0x000400

#ifdef EMIF1_CS0_INCLUDED
   EMIF1_CS0_MEMORY    : origin = 0x80000000, length = 0x10000000
#endif //EMIF1_CS0_INCLUDED
#ifdef EMIF1_CS2_INCLUDED
   EMIF1_CS2_MEMORY    : origin = 0x00100000, length = 0x00200000
#endif //EMIF1_CS2_INCLUDED
#ifdef EMIF1_CS3_INCLUDED
   EMIF1_CS3_MEMORY    : origin = 0x00300000, length = 0x00080000
#endif //EMIF1_CS3_INCLUDED
#ifdef EMIF1_CS4_INCLUDED
   EMIF1_CS4_MEMORY    : origin = 0x00380000, length = 0x00060000
#endif //EMIF1_CS4_INCLUDED
#ifdef EMIF2_CS0_INCLUDED
   EMIF2_CS0_MEMORY    : origin = 0x90000000, length = 0x10000000
#endif //EMIF2_CS0_INCLUDED
#ifdef EMIF2_CS2_INCLUDED
   EMIF2_CS2_MEMORY    : origin = 0x00002000, length = 0x00001000
#endif //EMIF2_CS2_INCLUDED

}

SECTIONS
{
#if BOOT_FROM_FLASH
   /* Allocate program areas: */
   .cinit              : > FLASHA_N      PAGE = 0, ALIGN(8)
   .pinit              : > FLASHA_N,     PAGE = 0, ALIGN(8)
   .text               : > FLASHA_N      PAGE = 0, ALIGN(8)
   codestart           : > BEGIN_FLASH       PAGE = 0, ALIGN(8)
   ramfuncs            : LOAD = FLASHA_N,
                         RUN = RAMLS_PROG,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         RUN_SIZE(_RamfuncsRunSize),
                         RUN_END(_RamfuncsRunEnd),
                         PAGE = 0, ALIGN(8)
   /* Initalized sections go in Flash */
   .econst             : > FLASHA_N      PAGE = 0, ALIGN(8)
   .switch             : > FLASHA_N      PAGE = 0, ALIGN(8)
   /* Allocate IQmath areas: */
   IQmath			: > FLASHA_N, PAGE = 0, ALIGN(8)            /* Math Code */
   IQmathTables		: > FLASHA_N, PAGE = 0, ALIGN(8)
   
   #ifdef CLA_BLOCK_INCLUDED
       /* CLA specific sections */
       Cla1Prog         : LOAD = FLASHA_N,
                          RUN = RAMLS_CLA_PROG,
                          LOAD_START(_Cla1funcsLoadStart),
                          LOAD_END(_Cla1funcsLoadEnd),
                          RUN_START(_Cla1funcsRunStart),
                          LOAD_SIZE(_Cla1funcsLoadSize),
                          PAGE = 0, ALIGN(8)
       .ebss            : > RAMGS_DATA ,    PAGE = 1
   #else
       .ebss            : >> RAMGS_DATA | RAMLS_DATA,    PAGE = 1 
   #endif //CLA_BLOCK_INCLUDED
   
#else
   codestart        : > BEGIN,     PAGE = 0
   ramfuncs         : > RAMLS_PROG      PAGE = 0
   .cinit           : > RAMLS_PROG,   PAGE = 0
   .pinit           : > RAMLS_PROG,     PAGE = 0
   .switch          : > RAMLS_PROG,     PAGE = 0
   .econst          : > RAMLS_PROG,    PAGE = 0
   /* Allocate IQ math areas: */
   IQmath			: > RAMLS_PROG,     PAGE = 0            /* Math Code */
   IQmathTables		: > RAMLS_PROG, PAGE = 0

   #ifdef CLA_BLOCK_INCLUDED
       /* CLA specific sections */
       Cla1Prog         : > RAMLS_CLA_PROG, PAGE=0
       .text            : >> RAMLS_PROG | RAMGS_PROG,   PAGE = 0
   #else
       .text            : > RAMLS_PROG,   PAGE = 0
   #endif //CLA_BLOCK_INCLUDED

   .ebss            : > RAMGS_DATA ,    PAGE = 1
 #endif //BOOT_FROM_FLASH

   .stack           : > RAMM0M1,     PAGE = 1
   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
   .esysmem         : > RAMD0D1,    PAGE = 1
   .cio             : > RAMLS_PROG, PAGE = 0

   #if defined(EMIF1_CS0_INCLUDED) && defined(EMIF2_CS0_INCLUDED)
      .farbss          : > EMIF1_CS0_MEMORY | EMIF2_CS0_MEMORY,      PAGE = 1
      .farconst        : > EMIF1_CS0_MEMORY | EMIF2_CS0_MEMORY,      PAGE = 1
   #elif !defined(EMIF1_CS0_INCLUDED) && defined(EMIF2_CS0_INCLUDED)
      .farbss          : > EMIF2_CS0_MEMORY,      PAGE = 1
      .farconst        : > EMIF2_CS0_MEMORY,      PAGE = 1
   #elif defined(EMIF1_CS0_INCLUDED) && !defined(EMIF2_CS0_INCLUDED)
      .farbss          : > EMIF1_CS0_MEMORY,      PAGE = 1
      .farconst        : > EMIF1_CS0_MEMORY,      PAGE = 1
   #else
      //No EMIF memory sections
   #endif //defined(EMIF1_CS0_INCLUDED) && defined(EMIF2_CS0_INCLUDED)

   #ifdef EMIF1_CS0_INCLUDED
      Em1Cs0           : > EMIF1_CS0_MEMORY,      PAGE = 1
   #endif //EMIF1_CS0_INCLUDED
   #ifdef EMIF2_CS0_INCLUDED
       Em2Cs0          : > EMIF2_CS0_MEMORY,      PAGE = 1
   #endif //EMIF2_CS0_INCLUDED
   #ifdef EMIF1_CS2_INCLUDED
       Em1Cs2          : > EMIF1_CS2_MEMORY,      PAGE = 1
   #endif //EMIF1_CS2_INCLUDED
   #ifdef EMIF1_CS3_INCLUDED
       Em1Cs3          : > EMIF1_CS3_MEMORY,      PAGE = 1
   #endif //EMIF1_CS3_INCLUDED
   #ifdef EMIF1_CS4_INCLUDED
       Em1Cs4          : > EMIF1_CS4_MEMORY,      PAGE = 1
   #endif //EMIF1_CS4_INCLUDED
   #ifdef MW_EMIF2_CS2_INCLUDED
       Em2Cs2          : > EMIF2_CS2_MEMORY,      PAGE = 1
   #endif //MW_EMIF2_CS2_INCLUDED
    
   #ifdef CLA_BLOCK_INCLUDED
       /* CLA C compiler sections */
       //
       // Must be allocated to memory the CLA has write access to
       //
       Cla1DataRam0		: > RAMLS_CLA_DATA, PAGE=1

       Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW,   PAGE = 1
       CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH,  PAGE = 1
       CLAscratch       :
                         { *.obj(CLAscratch)
                         . += CLA_SCRATCHPAD_SIZE;
                         *.obj(CLAscratch_end) } >  RAMLS_CLA_DATA,  PAGE = 1

       .scratchpad      : > RAMLS_CLA_DATA,       PAGE = 1
       .bss_cla		    : > RAMLS_CLA_DATA,       PAGE = 1
       .const_cla	    :  LOAD = FLASHA_N,
                           RUN = RAMLS_CLA_DATA,
                           RUN_START(_Cla1ConstRunStart),
                           LOAD_START(_Cla1ConstLoadStart),
                           LOAD_SIZE(_Cla1ConstLoadSize),
                           PAGE = 1
   #endif //CLA_BLOCK_INCLUDED

   #ifdef CPU1  
       /* The following section definitions are required when using the IPC API Drivers */ 
        GROUP : > CPU1TOCPU2RAM, PAGE = 1 
        {
            PUTBUFFER 
            PUTWRITEIDX 
            GETREADIDX 
            WRITEFLAG1CPU1
	    WRITEFLAG2CPU1
            READFLAG1CPU1
            READFLAG2CPU1
        }
        GROUP : > CPU2TOCPU1RAM, PAGE = 1
        {
            GETBUFFER :    TYPE = DSECT
            GETWRITEIDX :  TYPE = DSECT
            PUTREADIDX :   TYPE = DSECT
            WRITEFLAG1CPU2: TYPE = DSECT
            WRITEFLAG2CPU2: TYPE = DSECT
            READFLAG1CPU2:  TYPE = DSECT
            READFLAG2CPU2:  TYPE = DSECT
        }

   #else
       /* The following section definitions are required when using the IPC API Drivers */ 
        GROUP : > CPU2TOCPU1RAM, PAGE = 1 
        {
            PUTBUFFER 
            PUTWRITEIDX 
            GETREADIDX 
            WRITEFLAG1CPU2
            WRITEFLAG2CPU2
            READFLAG1CPU2			
            READFLAG2CPU2			
        }
        GROUP : > CPU1TOCPU2RAM, PAGE = 1
        {
            GETBUFFER :    TYPE = DSECT
            GETWRITEIDX :  TYPE = DSECT
            PUTREADIDX :   TYPE = DSECT
            WRITEFLAG1CPU1: TYPE = DSECT
            WRITEFLAG2CPU1: TYPE = DSECT
            READFLAG1CPU1 : TYPE = DSECT
            READFLAG2CPU1 : TYPE = DSECT
        }
   #endif //CPU1
        GROUP : > RAMGS_IPCBuffCPU1, PAGE = 1 
        {
            CPU1TOCPU2GSRAM
        }
        GROUP : > RAMGS_IPCBuffCPU2, PAGE = 1 
        {
            CPU2TOCPU1GSRAM
        }
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

#ifndef MW_F2837xD_MemoryMap_h_
#define MW_F2837xD_MemoryMap_h_

/* Below defines are used to allocate global shared memory in linker 
 * command file and for assign memory region to specific CPU. 
 * When you need to update global shared memory map, update through 
 * this file instead of linker command file. 
 * Copyright 2021 The MathWorks, Inc.*/

#if (BOOT_FROM_FLASH == 0) && defined(CLA_BLOCK_INCLUDED)
    #if defined(F28376D) || defined(F28374D)
        #define CPU1_RAMGS_PROG_START       0x011000
        #define CPU1_RAMGS_PROG_LENGTH      0x002000
        #define CPU2_RAMGS_PROG_START       0x016000
        #define CPU2_RAMGS_PROG_LENGTH      0x002000

        #define CPU1_RAMGS_DATA_START       0x00E000
        #define CPU1_RAMGS_DATA_LENGTH      0x003000
        #define CPU2_RAMGS_DATA_START       0x013000
        #define CPU2_RAMGS_DATA_LENGTH      0x003000
    #else
        #define CPU1_RAMGS_PROG_START       0x013000
        #define CPU1_RAMGS_PROG_LENGTH      0x002000
        #define CPU2_RAMGS_PROG_START       0x01A000
        #define CPU2_RAMGS_PROG_LENGTH      0x002000

        #define CPU1_RAMGS_DATA_START       0x00E000
        #define CPU1_RAMGS_DATA_LENGTH      0x005000
        #define CPU2_RAMGS_DATA_START       0x015000
        #define CPU2_RAMGS_DATA_LENGTH      0x005000
    #endif
#else
    #define CPU1_RAMGS_PROG_START       0x013000
    #define CPU1_RAMGS_PROG_LENGTH      0x000000
    #define CPU2_RAMGS_PROG_START       0x01A000
    #define CPU2_RAMGS_PROG_LENGTH      0x000000
    #if defined(F28376D) || defined(F28374D)
        #define CPU1_RAMGS_DATA_START       0x00E000
        #define CPU1_RAMGS_DATA_LENGTH      0x005000
        #define CPU2_RAMGS_DATA_START       0x013000
        #define CPU2_RAMGS_DATA_LENGTH      0x005000
    #else
        #define CPU1_RAMGS_DATA_START       0x00E000
        #define CPU1_RAMGS_DATA_LENGTH      0x007000
        #define CPU2_RAMGS_DATA_START       0x015000
        #define CPU2_RAMGS_DATA_LENGTH      0x007000
    #endif
#endif
#define RAMGS_IPC_CPU1_START       0x0C000
#define RAMGS_IPC_CPU1_LENGTH      0x001000
#define RAMGS_IPC_CPU2_START       0x0D000
#define RAMGS_IPC_CPU2_LENGTH      0x001000
#endif

Hi Zvi,

After looking at the cmd files, I see that you've used the entirety of Flash sectors A to N for your flash use, however as noted per the errata advisory in the example linker cmd file, FLASHN_RSVD must be protected (origin = 0x0BFFF0, length = 0x000010) to avoid "Memory Prefetching: Beyond Valid Memory". Is it possible to avoid programming this section for your application, try to change sections used?

Let me know about this.

Charles 

Hello

Please send me this errata

Zvi,

Here is a link to the errata for the TMS320F2837xD. The advisory on the prefetching can be found on page 32, it can also be found in the example files (2837xD_FLASH_lnk_cpu1.cmd in the device's LED example where it discusses FLASHN_RSVD).

Thanks,

Charles

Thanks, I am using F28379D and this errata is not for this device

And why is it that Core1 is flashed ok but not Core2 ?

Zvi,

Will need a bit more time to go over the files presented, I've done a check on the memory ranges, and they seem fine. As far as the errata is concerned, will need to consult with others on this. Will get back to you as soon as possible.

Thanks,

Charles

Hi Zvi,

Testing the linker cmd files, will try to reproduce the issue with debug. This is likely a programming issue.

To note, the errata does apply to the F28379D device as well. Will see about having the app note updated.

Thanks and regards,

Charles

Hi Charles,

Please feel free to update me if any progress was made regarding the Core2 serial programming.

Zvi.

Hi Zvi,

In order to make progress, can you send the .out file here or in the messages? I will see if it affects my device and what can be done.

Thanks,

Charles

Hello Charles,

I cannot send you our company IP.

Please try to debug it with a different out file

Hi Zvi,

Understandable. I'll try to debug it with a different .out file and get back to you within the next day. 

Charles

Hi Zvi,

Charles asked me to take a look at this post.

Quick question: I noticed below in your linker cmd file.  Could you check your map file to see what is assigned at address 0x220026 that you reported?  

#if defined(EMIF1_CS0_INCLUDED) && defined(EMIF2_CS0_INCLUDED)
.farbss : > EMIF1_CS0_MEMORY | EMIF2_CS0_MEMORY, PAGE = 1
.farconst : > EMIF1_CS0_MEMORY | EMIF2_CS0_MEMORY, PAGE = 1
#elif !defined(EMIF1_CS0_INCLUDED) && defined(EMIF2_CS0_INCLUDED)
.farbss : > EMIF2_CS0_MEMORY, PAGE = 1
.farconst : > EMIF2_CS0_MEMORY, PAGE = 1
#elif defined(EMIF1_CS0_INCLUDED) && !defined(EMIF2_CS0_INCLUDED)
.farbss : > EMIF1_CS0_MEMORY, PAGE = 1
.farconst : > EMIF1_CS0_MEMORY, PAGE = 1
#else
//No EMIF memory sections
#endif //defined(EMIF1_CS0_INCLUDED) && defined(EMIF2_CS0_INCLUDED)

May be some initialized content is mapped there and hence flash kernel is trying to program it (which will fail since it is not flash address).

Thanks and regards,
Vamsi

Hello Vamsi,

    I just looked at the map file and there are no sections: .farbss nor .farconst  .

    We use same linker cmd file for core 1 and there are no issues while programming it ..

Best regards, Zvi.

Hi Zvi,

I am currently not able to replicate the issue. Would you be available to have a call over it soon so that we can diagnose it together?

Thanks,

Charles