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TMS320F280049C: I2C causes a instruction-trap interrupt

Cherry Zhou
Mastermind 22235 points

Part Number: TMS320F280049C

Hi team,

Here's an issue from the customer may need your help:

When using IIC, an illegal instruction-trap interrupt handler may be entered during power-up initialization and parameter reading. As the following figure shows:

The behavior no longer occurs after replacing one E2PRROM chip.

However, the customer would like to figure out why the chip's illegal instruction trap interrupt handler is affected. If it is because of the code, why does not trigger every run, but only after a period of power down? If it is not a code problem, is it possible for external levels to cause the problem? Could you help check it? Thanks.

Best Regards,

Cherry

  • 0
    TI__Mastermind 19795 points

    Hi Cherry,

    Thanks for your question. Illegal instruction trap can be caused by any of the below causes (from the C28x TMS320C28x CPU and Instruction Set Reference Guide).

    Given the fact it only happens after power down, it's possible there's a 32-bit assembly instruction trying to access using the @SP register addressing mode (last bullet), or even using illegal addressing modes (first bullet).

    This can be done by stepping through the code and determining where it is occuring.

    The fact that this is happening with external EEPROM means this is could be an access request to an address space that doesn't exist in the C28x (but does exist in the EPROM).

    Regards,

    Vince