TMS320F280023: Memory Power On Self Test (MPOST) configuration/result error

Additional info...

In the F28002x TRM section 4.7.10.2 Boot Mode and MPOST Status it states to see "C2000 Memory Power-On Self-Test (M-POST) Application Report" which provides Table A-2 M-POST Status which gives a return value of 0xFFFFFFFF for a successful test.

However, in looking through the F28002x_ROM source files I found the following in cpu1brom_pbist.h that has different return values and states 0xFAABDEED is the return value for a successful test.

// ERROR CODES - Used as return values
#define PBIST_ALWAYSFAIL_TIMEOUT_ERROR 0xFF00FF00U // Expected fail test did not complete
#define PBIST_ALWAYSFAIL_INCORRECT_OPERATION 0xFF11FF01U
#define PBIST_DOUBLEINT_TIMEOUT_ERROR 0xFF22FF02U
#define PBIST_MEMORYTEST_TIMEOUT_ERROR 0xFF33FF03U

#define PBIST_MEMORY_TEST_FAIL_ERROR 0xFF44FF04U

#define PBIST_MEMORY_LS_INITDONE_ERROR 0xFFAAFF0AU
#define PBIST_MEMORY_GX_INITDONE_ERROR 0xFFBBFF0BU
#define PBIST_MEMORY_M0M1_INITDONE_ERROR 0xFFCCFF0CU
#define ISOLATE_MEM_INIT_ERROR 16

#define PBIST_MASK_KEEP_ERROR_CODE_UPPER 0xFFFF0000U

#define PBIST_MEMORY_TEST_IN_PROGRESS 0xFAAB1234UL // Return status while memory testing is in progress
#define PBIST_MEMORY_TEST_PASS 0xFAABDEEDUL // Marker for successful completion of mem test

While I have not been able to get MPOST to run on the LaunchXL board in Debug, programing the OTP as specified in the original post, and power cycling the board without the emulator, the memory test does appear to run causing a 5 seconds or so and a check of 0x00000006 does provide a value of 0xFAABDEED.   Running the same program on a second board that does not have GPREG2 programed does not have the delay and does not have a value of 0xFAABDEED at 0x00000006.  Can you please confirm that the table referenced in the TRM is incorrect and that cpu1brom_pbist.h is correct?

Also, is there a way to get MPST to run in Debug?  I have programed the EMU_Boot locations as follows:

0xD00 = 0xFFFFFFFF

0xD02 = 0x5AFFFF3F

0xD04 = 0xFFFFFFFF

0xD06 = 0xFFFFFFFF

After setting the above values I selected CPU Reset and Resume but it hits a ESTOP0 in the boot rom.

Thanks,

Don

Hi,

The subject matter expert will get back to you later today.

Thanks & Regards,

Santosh

Hi Don,

The application report is showing the error codes for F28004x device. For F28002x you can refer to the error codes from header file. I will see how to improve the documentation to provide more clarity.

Regarding the status being 0x00000000 - your OTP configuration to enable pbist is correctly configured and the fact that booting takes time confirms this. so we can conclude that pbist has executed.

The status might have go overwritten by gel file or some other code. to eliminate the role of gel file can you remove it before launching the target configuration and connecting to the CPU ?

Thanks for the clarification on the documentation, it does appear to be functioning correctly outside of debug.  Any thoughts on why I can't get it to run in debug mode?  From my understanding, when restarting in debug mode it looks to the emulation locations and not the OTP memory.  I have set the emulation locations as follows but continue to run into an ESTOP0 in the boot rom at location 0x3F4751.  Any idea why it its the ESTOP after setting 0xD02?

0xD00 = 0xFFFFFFFF

0xD02 = 0x5AFFFF3F

0xD04 = 0xFFFFFFFF

0xD06 = 0xFFFFFFFF

Thanks, that is what I understood as well.  However, I thought that after going into debug and setting location 0xD02 you could do a CPU reset which would simulate a POR?  If that is not the case is there anyway to test and see the MPOST results in Debug?

Thanks,

Don

Thank you.