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TMS320F28374D: NMI and ITRP interrupts management

Stefan Lintner
Expert 5245 points

Part Number: TMS320F28374D
Other Parts Discussed in Thread: SYSBIOS

HI Team,

Customer is looking into the management of the MNI and ITRP interrupts to try to add some ways to log those when they arise.

Could you please provide some documentation for the default handler of those interrupts?

BR,
Stefan

  • 0
    TI__Guru* 95315 points

    Stefan,

             Both NMI and ITRAP are documented in the TRM (see pages 109 & 110 of SPRUHM8I). ITRAP is further explained in SPRU430. We don’t have any documentation beyond these two.

  • 0 in reply to Hareesh Janakiraman
    TI__Expert 5245 points

    Thank you Hareesh!

    Customer would actually like to identify the reset cause at startup.

    They am facing some difficulties to understand the datasheet on the delphinos (TMS320F2837xD Dual-Core Microcontrollers. spruhm8i.pdf)

    Looking at the NMIFLG and NMISHDFLG, they do not fully understand what is condition that generate the following flags

    - OVF

    - CLBNMI

    - PIEVECTERR

     

    Also they would like to confirm an understanding.

    If CPU2 WDG has triggered the reset then the WDRSn bit of the RESC register will be set and the CPU2WDRSn bit of the NMISHDFLG register.

    If CPU1 WDG has triggered the reset then only the WDRSn bit of the RESC register will be set.  

    Is that a correct assumption?

    BR,
    Stefan

  • 0 in reply to Stefan Lintner
    TI__Guru* 95315 points

    Stefan,

       I need to research this. Give me a few days.

  • 0 in reply to Stefan Lintner
    TI__Guru* 95315 points
    Stefan Lintner said:
    Customer would actually like to identify the reset cause at startup.

    The RESC register should be examined for this. See page 393 of the TRM.

    Stefan Lintner said:
    Looking at the NMIFLG and NMISHDFLG, they do not fully understand what is condition that generate the following flags

    OVF - This bit is a RESERVED bit. This will be fixed in the next update of the TRM.

    CLBNMI - Agree this is not documented clearly. I am still researching this. 

    PIEVECTERR - This is explained in page 110 & 234. Please let me know if it is not clear.

    Stefan Lintner said:
    If CPU2 WDG has triggered the reset then the WDRSn bit of the RESC register will be set and the CPU2WDRSn bit of the NMISHDFLG register.

    CPU2 WD cannot reset the device. "CPU2's watchdog reset (CPU2.WDRS) produces a CPU2.SYSRS and triggers an NMI on CPU1." CPU2WDRSn bit of the NMIFLG register will be set upon a CPU2 WD reset.

    Stefan Lintner said:
    If CPU1 WDG has triggered the reset then only the WDRSn bit of the RESC register will be set.  

    Correct.

  • 0 in reply to Hareesh Janakiraman
    TI__Expert 5245 points

    Hi Hareesh,

    Thank you for your input!

    Looking forward to info about CLBNMI!

    In the meantime following questions came up at customer:

    will RESC, NMIFLG and NMISHDFLG have the same value on CPU1 and CPU2 or could they be different?

     

    Another confirmation question for NMIFLG  bit CPU2HWBISTERR/ CPU1HWBISTERR  .

    Can you give a bit of explanation when those bits will be set.

    Is there a default configuration of the interrupt handler ? If so, what is it ?

    BR,
    Stefan

  • 0 in reply to Stefan Lintner
    TI__Guru 55095 points
    Stefan Lintner said:

    Another confirmation question for NMIFLG  bit CPU2HWBISTERR/ CPU1HWBISTERR  .

    Can you give a bit of explanation when those bits will be set.

    If you use HWBIST to run diagnostics on the CPUs and an error is detected, one of these flags gets set depending on which CPU the error was detected. For more information about these flags and HWBIST in general, you can see this app note.

    Whitney

  • 0 in reply to Whitney Dewey
    TI__Guru 52220 points

    The CLB’s HLC module can generate an NMI instead of a normal interrupt.

    You can enable this by:

    But this is not available on the device you are using.

    If it is mentioned in the registers then it is missed item in the document for F2837xD.

    Nima

  • +1 in reply to Nima Eskandari
    TI__Guru* 95315 points
    Stefan Lintner said:
    will RESC, NMIFLG and NMISHDFLG have the same value on CPU1 and CPU2 or could they be different?

    They could be different.

    Stefan,

         I believe we have answered all your questions and hence closing the post.

  • 0 in reply to Hareesh Janakiraman
    TI__Expert 5245 points

    Hi Hareesh,

    thank you! two more questions:

    Regarding SYSBIOS, could you point me to the documentation on default ISR implementation for the non maskable interrupts.

    Is  a hwi_create on the NMI possible? it seems to fail.

    BR,
    Stefan

  • +1 in reply to Stefan Lintner
    TI__Guru* 95315 points

    Stefan,

        I suggest closing this post and creating a new post with the appropriate title. This will make future searches easy and also enable better archival/analytics. Thanks.