TMS320F280025C: SOC configuration

Hi,

I am developing a digital regulation, and I've an issue with my Start Of Conversion configuration, I have to perform an averaging of the self current.

You can see a drawing.

I'm on UP DOWN count for TBCTR register. 

Is it possible to generate different SOCs for the same TBCTR counter period?

void adc_init(void)
{
    SetVREF(ADC_ADCA, ADC_INTERNAL, ADC_VREF3P3);
    EALLOW;
    /// Set ADCCLK divider to /2
    AdcaRegs.ADCCTL2.bit.PRESCALE = 2;
    /// Interrupt pulse generation occurs at the end of the conversion.
    AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;
    /// Power up the ADC, enable ADC
    AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
    /// Delay for power.
    DELAY_US(1000);

    /// Enable the ADC Start Of Conversion Pulse
    EPwm1Regs.ETSEL.bit.SOCBEN = 1;
    /// Generate  pulse at TBCTR equal 0.
    EPwm1Regs.ETSEL.bit.SOCBSEL = 1;
    /// Generate the EPWM1SOCB pulse on the first event.
    EPwm1Regs.ETPS.bit.SOCBPRD = 1;

    /// SOC0 will convert ADCINC6 : MU_TRAC_BATT_PCH_FLT signal
    AdccRegs.ADCSOC0CTL.bit.CHSEL = 6;
    /// Time total for one sample equal 550ns
    AdccRegs.ADCSOC0CTL.bit.ACQPS = 8;
    /// Trigger on ePWM1 ADCSOCB
    AdccRegs.ADCSOC0CTL.bit.TRIGSEL = 6;
    
    EDIS;
}

void epwm_init_spwm_u(void)
{
    EALLOW;
    /// Disable counting
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
    EDIS;

    /// Setup counter mode
    /// Configure pre-scaler and high speed pre-scaler, divide by 1.
    EPwm1Regs.TBCTL.bit.CLKDIV = 0;
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;
    /// Up Down count mode.
    EPwm1Regs.TBCTL.bit.CTRMODE = 2;

    /// Setup time base counter.
    /// Immediate mode, a write or read to the TBPRD register accesses the active register.
    EPwm1Regs.TBCTL.bit.PRDLD = 1;
    EPwm1Regs.TBPRD = TBPRD_VALUE;
    /// Clear counter
    EPwm1Regs.TBCTR = 0;

    /// Phase settings
    /// Select EPWMxSYNCOUT signal when TBCTR = 0 for master signal.
    EPwm1Regs.EPWMSYNCOUTEN.bit.ZEROEN = 1;
    /// Do not load the time base counter (TBCTR) from the time base phase register (TBPHS).
    EPwm1Regs.TBCTL.bit.PHSEN = 0;
    /// Synchronization event is ignored.
    EPwm1Regs.TBPHS.bit.TBPHS = 0;

    /// Setup counter compare.
    /// Immediate mode, all writes and reads directly access the active register for immediate actions.
    EPwm1Regs.CMPCTL.bit.SHDWAMODE = 1;
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = 1;
    /// To have 50% duty cycle
    EPwm1Regs.CMPA.bit.CMPA = CMP_VALUE;
    EPwm1Regs.CMPB.bit.CMPB = CMP_VALUE;

    /// Actions
    /// When TBCTR = CMPA on UP count, force EPWMxA output low.
    EPwm1Regs.AQCTLA.bit.CAU = 1;
    /// When TBCTR = CMPA on DOWN count, force EPWMxA output low.
    EPwm1Regs.AQCTLA.bit.CAD = 2;

    /// Actions
    /// When TBCTR = CMPB on UP count, force EPWMxB output high.
    EPwm1Regs.AQCTLB.bit.CBU = 2;
    /// When TBCTR = CMPB on DOWN count, force ePWMxB output high.
    EPwm1Regs.AQCTLB.bit.CBD = 1;

    /// Enable counting
    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
    EDIS;
}

I would like to generate SOC0 at TBCTR = 0, then SOC1 at CMPA incrementing then SOC2 at TBPRD then SOC3 at CMPA decrementing then after make my average by triggering an interrupt at EOC3 to come my corresponding ADCRESULT. Is this possible? I see that by the register ETSEL.SOCBSEL I can configure a state of triggering of SOC, but I would like to link a SOCx to a particular trigger on this ramp.

How can I do this please?

Here my code :

Thanks

Damien