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TMS320F2812: SPI tansmission FIFO

Allen Gong
Prodigy 70 points

Part Number: TMS320F2812

In my application ,F2812 works as a SPI slave whose baudrate is 500k。Every 4ms  a master talks with it once by exchanging 6 words.FIFO of F2812's SPI is enabled to save cpu's  load.The reception fifo is checked every 1 ms,all reception fifo are read out after successful reception and transmission fifo is reset and reloaded with 1~6。word "0" is written to SPIDAT as the first transmission data,it just works fine as 1~5 will be transmitted afterwards when the cpu runs freely.When the code is loaded with a usb emulator and executed  afterwards,data transmitted out are 2~6.It seems that data are transmitted from the second FIFO when the code is runned via usb emulator.What would be my problem?How to fix it?

Thanks for your time!

  • 0
    TI__Mastermind 30541 points

    Hello Allen,

    When you mention "the CPU runs freely", do you mean the code boots and runs from flash?

    How does your code ensure the SPI is not in the middle of a transaction when you reset and reload the FIFO? 

  • 0 in reply to Gus Martinez
    Prodigy 70 points

    Yes,"the cpu runs freely" means code runs from flash.    Every 4ms two cpus exchanges data once, every 1 ms  the reception FIFO is checked to make sure complete data has been exchanged and the FIFO is reset after successful exchange. I think  it ensured the successful transimission with a successful reception. if it happened to be in the middle of transimission,it should happen only occasionally,yet the transimission fifo is always one word  ahead when code runs with a emulator.

     Thank you for your reply!

  • 0 in reply to Gus Martinez
    Prodigy 70 points

    Yes,"the cpu runs freely" means code runs from flash.    Every 4ms two cpus exchanges data once, every 1 ms  the reception FIFO is checked to make sure complete data has been exchanged and the FIFO is reset after successful exchange. I think  it ensured the successful transimission with a successful reception. if it happened to be in the middle of transimission,it should happen only occasionally,yet the transimission fifo is always one word  ahead when code runs with a emulator.

     Thank you for your reply!

  • 0 in reply to Allen Gong
    TI__Mastermind 30541 points
    Allen Gong said:
    the FIFO is reset after successful exchange

    I don't really understand why the FIFO needs to be reset after successful data exchange, but maybe that's not the source of the problem.

    Allen Gong said:
    the transimission fifo is always one word  ahead when code runs with a emulator

    How are you seeing this error in the data? Are you monitoring the SPI bus with a logic analyzer? Are you using a watch window in CCS to view some MCU buffer content? The description of the symptoms is not very clear.

    Please note that when running CCS, actions such as polling memory, watch windows, breakpoints, etc. momentarily halts the CPU. It is possible this CCS activity is affecting the operation of your application. You can try:

    - Enable Free Run in the SPIPRI register

    - Use Real-time mode in CCS (video)