TMDSCNCD28388D: LWIP program out of RAM memory

Hi, 

Which sections are not able to fit in the memory? Is it only the .bss section? 

Did you try allocating it to multiple sections of memory?

Can you share the linker cmd file that you are using? 

Best Regards

Siddharth

Hello Siddharth.
I'm wondering if the "Bit Band RAM Zone" in the memory mapping of the CM core mentioned in tms320f28386d-1949390.pdf can be used by the user.
.bss and .binit are failing for memory allocation.
The cause is .bss .common:memp_memory_PBUF_POOL_base occupies 243kbyte capacity.
I think that assigning this part to "Bit Band RAM Zone" will solve the problem.
However, in the default .cmd file when creating a SYS/BIOS project, there is no description of memory allocation for the "Bit Band RAM Zone" part.
That's why I asked because I didn't know if I could use it.
Below is the description of the .cmd file.

It is assumed to read from flash, so it has been changed from the default.
thank you.

/*
* Copyright (c) 2018, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/

MEMORY
{
/* Flash sectors */
CMBANK0_RESETISR : origin = 0x00200000, length = 0x00000008 /* Boot Entry */
CMBANK0_SECTOR0 : origin = 0x00200008, length = 0x00003FF7
CMBANK0_SECTOR1 : origin = 0x00204000, length = 0x00004000
CMBANK0_SECTOR2 : origin = 0x00208000, length = 0x00004000
CMBANK0_SECTOR3 : origin = 0x0020C000, length = 0x00004000
CMBANK0_SECTOR4 : origin = 0x00210000, length = 0x00010000
CMBANK0_SECTOR5 : origin = 0x00220000, length = 0x00010000
CMBANK0_SECTOR6 : origin = 0x00230000, length = 0x00010000
CMBANK0_SECTOR7 : origin = 0x00240000, length = 0x00010000
CMBANK0_SECTOR8 : origin = 0x00250000, length = 0x00010000
CMBANK0_SECTOR9 : origin = 0x00260000, length = 0x00010000
CMBANK0_SECTOR10 : origin = 0x00270000, length = 0x00004000
CMBANK0_SECTOR11 : origin = 0x00274000, length = 0x00004000
CMBANK0_SECTOR12 : origin = 0x00278000, length = 0x00004000
CMBANK0_SECTOR13 : origin = 0x0027C000, length = 0x00004000

C1RAM : origin = 0x1FFFC000, length = 0x00001FFF
C0RAM : origin = 0x1FFFE000, length = 0x00001FFF

/* Part of S0, BOOT rom will use this for stack */
BOOT_RSVD : origin = 0x20000000, length = 0x00000800
S0RAM : origin = 0x20000800, length = 0x0000F7FF
E0RAM : origin = 0x20010000, length = 0x00003FFF

CPU1TOCMMSGRAM0 : origin = 0x20080000, length = 0x00000800
CPU1TOCMMSGRAM1 : origin = 0x20080800, length = 0x00000800
CMTOCPU1MSGRAM0 : origin = 0x20082000, length = 0x00000800
CMTOCPU1MSGRAM1 : origin = 0x20082800, length = 0x00000800
CPU2TOCMMSGRAM0 : origin = 0x20084000, length = 0x00000800
CPU2TOCMMSGRAM1 : origin = 0x20084800, length = 0x00000800
CMTOCPU2MSGRAM0 : origin = 0x20086000, length = 0x00000800
CMTOCPU2MSGRAM1 : origin = 0x20086800, length = 0x00000800
}

SECTIONS
{
.resetisr : > CMBANK0_RESETISR
.vftable : > CMBANK0_SECTOR0 /* App vector table Flash */
.vtable : > S0RAM /* App vector table RAM */
.text : >> CMBANK0_SECTOR0 | CMBANK0_SECTOR1 | CMBANK0_SECTOR2 |
CMBANK0_SECTOR3 | CMBANK0_SECTOR4 | CMBANK0_SECTOR5
.cinit : > CMBANK0_SECTOR0 | CMBANK0_SECTOR1 | CMBANK0_SECTOR2 |
CMBANK0_SECTOR3 | CMBANK0_SECTOR4 | CMBANK0_SECTOR5
.pinit : > CMBANK0_SECTOR0 | CMBANK0_SECTOR1
.binit : > CMBANK0_SECTOR0 | CMBANK0_SECTOR1
.switch : >> CMBANK0_SECTOR0 | CMBANK0_SECTOR1
.sysmem : > S0RAM
.stack : > C1RAM
.ebss : > C1RAM
.econst : >> CMBANK0_SECTOR0 | CMBANK0_SECTOR1 | CMBANK0_SECTOR2 |
CMBANK0_SECTOR3 | CMBANK0_SECTOR4 | CMBANK0_SECTOR5
.esysmem : > C1RAM
.data : > S0RAM
.bss : > S0RAM
.const : {} LOAD = CMBANK0_SECTOR0 | CMBANK0_SECTOR1 | CMBANK0_SECTOR2 |
CMBANK0_SECTOR3 | CMBANK0_SECTOR4 | CMBANK0_SECTOR5 ,
RUN = S0RAM,
LOAD_START(constLoadStart),
LOAD_SIZE(constLoadSize),
LOAD_END(constLoadEnd),
RUN_START(constRunStart),
RUN_SIZE(constRunSize),
RUN_END(constRunEnd)

MSGRAM_CM_TO_CPU1 : > CMTOCPU1MSGRAM0, type=NOINIT
MSGRAM_CM_TO_CPU2 : > CMTOCPU2MSGRAM0, type=NOINIT
MSGRAM_CPU1_TO_CM : > CPU1TOCMMSGRAM0, type=NOINIT
MSGRAM_CPU2_TO_CM : > CPU2TOCMMSGRAM0, type=NOINIT

.TI.ramfunc : {} LOAD = CMBANK0_SECTOR0 | CMBANK0_SECTOR1,
RUN = S0RAM,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
ALIGN(8)

}

Hi , 

I am not sure  of Bit Band RAM Zone. 

You can try to combine multiple RAM sections to allocate the .bss,

for e.g:

.bss : > S0RAM | E0RAM 

Best Regards

Siddharth

Hello Siddharth.
Bit Band Ram zone is mentioned on his 250p in PDF(https://www.ti.com/lit/gpn/tms320f28388d).
As described in this PDF, S0RAM to S3RAM each have a capacity of 16KByte, and E0RAM also has a capacity of 16KByte, so it is far from the required capacity.
Therefore, I would like to allocate memory using both the Bit Band Ram zone, which has a capacity of 32MByte, and SRAM.
thank you.

Hi, 

I haven't used the Bit Band Ram zone before, so cannot comment on it. 

You can try it out. In the meantime , I will try to get more details about it.

Best Regards

Siddharth

Hi,
Thank you for answering.
I am editing the linker file now, but I would like to map the .bss section and the .common section separately within the .bss section. Is this possible?
For the time being, place all .bss sections in the Bit Band Ram Zone to check the operation.
I would appreciate it if you could let me know if you have more information.
thank you.

Hi, 

I don't think you can split the .bss section.  

Is the data for .bss common section located in a single file or spread across files? 

Best Regards

Siddharth

hello.

I mapped the Bit Band Ram Zone to the .cmd file.

After that, I specified to map the .bss section to S0RAM and Bit Band Ram Zone.

It was mapped as shown in the image below and the project was able to build successfully.

In order to check the operation, I debugged after building, but an error like this thread occurred and debugging did not proceed.
I'm stuck in a state where I can't set breakpoints and pause debugging.
I have tried the solutions in the thread but have not been able to resolve the issue.

I don't know how to solve it because I'm debugging under an environment using SYS/BIOS.

thank you.

Hi, 

Will forward this query to the CCS team so that they can assist you in debugging this furhter.  

Best Regards

Siddharth

Hello

ryo tsuchiya said:

In order to check the operation, I debugged after building, but an error like this thread occurred and debugging did not proceed.
I'm stuck in a state where I can't set breakpoints and pause debugging.

There are several errors in the your screenshot. The error about lack of breakpoint resources, I believe that is a symptom of a different issue and not the root cause. The F28388D should have more hardware breakpoint resources than eariler F28x devices.

When did these breakpoint resource errors occur? Right after you pressed "Debug"? Or are you manually trying to set additional breakpoints yourself?

The more serious issue and root cause is likely the Device is locked up in Hard Fault or in NMI error. Please see the below article for more details:

https://dev.ti.com/tirex/explore/node?node=A__ANoamrIZPWD2-6T-NDDWGg__ccs_devtools__FUz-xrs__LATEST

Search for the section "Device is locked" in the above article.

Do you have any issues with other applications, like the standard examples from C2000Ware?

Thanks

ki

Hi.
When I debugged again, it looked like the first image immediately after starting debugging, then restarted the CM core and executed in the order of CPU1 and CM core.

After that, when I stopped each debugging operation, the referenced address became 0 as in the second image.

When I debugged each of them in the SYS/BIOS Typical project without editing, I was able to confirm that they were working properly.

What problems might you have with your project?

I would like to continue to investigate the cause.

thank you.

ryo tsuchiya said:

When I debugged each of them in the SYS/BIOS Typical project without editing, I was able to confirm that they were working properly.

It appears that the modified project has some issues where it is putting the target in a bad state, causing the various breakpoint issues. It is beyond my expertise to debug the modified project. I'll have the device experts comment further.

Hi, 

You can try to single step and see the execution flow. Not sure what is causing this issue.

Best Regards

Siddharth

Hello.

The following error occurs when debugging, is there any problem with this?

Cortex_M4_0: Only CPU1 on-chip Flash Plugin can configure clock for CPU1, CPU2 and CM Flash operations. Plugin automatically configures PLL when CPU1 Flash operations are invoked. operation in the current session, they should click on 'Configure Clock' button in CPU1's on-chip Flash Plugin before invoking CPU2 and CM Flash operations. When this button is used, Flash Plugin will configure the clock for CPU1/CPU2 at 190MHz and CM at 95MHz using INTOSC2 as the clock source. Plugin will leave PLL config like this and user application should configure the PLL as required by application.

Also, the .out file of another project is assigned to CPU1 and CM core and executed, but at that time debugging is started while CM core operation is in progress.
Is there any problem with that matter?
thank you.

Hi, 

Once you load the CM core with the .out file , you can try to set some breakpoints and see if the execution continues. You will have to narrow down the location/code/function which is causing the device to go into Hard Fault.

Best Regards

Siddharth

This is a naive question, but which is better, NDK or LWIP, when TCP communication is currently performed using RTOS?

Hi,

Please note that TI NDK is no longer actively supported and hence there will be no technical analysis provided for any TI NDK issues.  

If you are using RTOS, would suggest you to use FreeRTOS.

Best Regards

Siddharth

When using both the CM core and the C28x core, is it better to configure the C28x core to use SYSBIOS and the CM core to use FreeRTOS?
Or is it better to configure everything with FreeRTOS?

Also, I couldn't find information about FreeRTOS for 28388, so please provide it.

thank you.

Hi, 

I think its better to have FreeRTOS on both the cores. 

Currenty there is no example of LWIP with FreeRTOS in C2000Ware. However FreeRTOS support was added for C28x and CM core in the latest release of C2000Ware (v4.02.00.00) . There are few demos included for F28388. 

Best Regards

Siddharth