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TMS320F28379D: Question on NMI about NMIFLGFRC[CPU2WDRSn] bit setting

Julia Li
Expert 4755 points

Part Number: TMS320F28379D

Hi team,

I ask this for our customer.

1. Customer read 3.5.3.5 in TRM and want to know if customer set the NMIFLGFRC[CPU2 DRSn] bit to 1, will it cause the NMI of the CPU1 to interrupt and then cause the device to reset? 

2. If customer sets the NMIFLGFRC[CPU2 DRSn] bit to 1, will it cause the watchdog reset of CPU2 immediately? Or will it enable the watchdog of CPU2, then wait for the watchdog counter to overflow, and then reset the watchdog of CPU2?

3. Which bit of the CpuSysRegs.RESC register will be set to 1 if the above mentioned reset occurs? Is it the WDRSn bit or the NMIWDRSn bit?

Could you please kindly help to check it? Thanks!

Best, 

Julia

  • +1
    TI__Guru* 95315 points
    Julia Li said:
    1. Customer read 3.5.3.5 in TRM and want to know if customer set the NMIFLGFRC[CPU2 DRSn] bit to 1, will it cause the NMI of the CPU1 to interrupt and then cause the device to reset?

    It would indeed assert NMI on CPU1 (NMIFLG.CPU2WDRSn bit would be set). However, this will *not* cause a device reset.

    Julia Li said:
    2. If customer sets the NMIFLGFRC[CPU2 DRSn] bit to 1, will it cause the watchdog reset of CPU2 immediately? Or will it enable the watchdog of CPU2, then wait for the watchdog counter to overflow, and then reset the watchdog of CPU2?

    No, that would not cause a watchdog reset. Nor would it enable the WD of the CPU2. The bits in the NMIFLGFRC register are meant to simulate the events. This can be used to verify the response of the application to the simulated condition.

    Julia Li said:
    3. Which bit of the CpuSysRegs.RESC register will be set to 1 if the above mentioned reset occurs? Is it the WDRSn bit or the NMIWDRSn bit?

    WDRSn. Note that Watchdog and NMI-Watchdog are two different modules.

  • 0 in reply to Hareesh Janakiraman
    TI__Expert 4755 points

    Hi Hareesh,

    Here are some additional questions from customer:

    Hareesh Janakiraman said:
    It would indeed assert NMI on CPU1 (NMIFLG.CPU2WDRSn bit would be set). However, this will *not* cause a device reset.

    I don't particularly understand this part. What will happen after asserting NMI? So is it means that after NMIFLG.CPU2WDRSn is set to 1, it will enter the NMI interrupt of CPU1. If the NMI interrupt does not clear this bit and wait for the NMI watchdog timer of CPU1 to overflow, device will be reset?

    Hareesh Janakiraman said:
    WDRSn. Note that Watchdog and NMI-Watchdog are two different modules.

    Looking at the description of the datasheet, it is not the reset caused by the watchdog, but the reset caused by the NMI watchdog? I want to know if my understanding is correct? Why should the WDRSn bit be 1 instead of the NMIWDRSn bit?

    Best, 

    Julia

  • 0 in reply to Julia Li
    TI__Guru* 95315 points

    Julia,

       I need to research this a bit. Will get back to you in a day or two.

  • 0 in reply to Hareesh Janakiraman
    TI__Expert 4755 points

    Hi Hareesh,

    Is there any update on this case? Thanks!

    Best, 

    Julia

  • 0 in reply to Julia Li
    TI__Guru* 95315 points
    Julia Li said:
    If the NMI interrupt does not clear this bit and wait for the NMI watchdog timer of CPU1 to overflow, device will be reset?

    Yes, in that case, a reset will be asserted. 

    Julia Li said:
    Why should the WDRSn bit be 1 instead of the NMIWDRSn bit?

    I agree the TRM description is very confusing. I will come up with better wording.

  • 0 in reply to Hareesh Janakiraman
    TI__Expert 4755 points

    Hi Hareesh,

    Hareesh Janakiraman said:
    I agree the TRM description is very confusing. I will come up with better wording.

    Thanks for your reply! I want to double check with you that if this means WDRSn bit should be 1 when above mentioned reset occurs? 

    Hareesh Janakiraman said:
    Yes, in that case, a reset will be asserted. 

    Based on the description in this part of the TRM below, I wonder if this proves that this is not an NMI-caused reset? Thanks!

    Best, 

    Julia

  • 0 in reply to Julia Li
    TI__Guru* 95315 points

    Julia,

         This is Thanksgiving week and many people are on vacation. Please expect some delay in responses.

  • 0 in reply to Hareesh Janakiraman
    TI__Expert 4755 points

    Hi Hareesh,

    Is there an update on this question? Thanks!

    Best, 

    Julia

  • 0 in reply to Julia Li
    TI__Guru* 95315 points

    Julia,

          I need to work with the Design team to confirm my understanding and also come up with better wordings for the TRM. Currently, I am  unable to spend much time on this. If this is preventing application development, I can look into prioritizing this. Please feel free to email me offline.

  • 0 in reply to Hareesh Janakiraman
    TI__Expert 4755 points

    Hi Hareesh,

    Customer still need us check this case because of their end customer's demand, could you please help on it? Thanks!

    Best, 

    Julia

  • 0 in reply to Julia Li
    TI__Guru* 95315 points

    Julia,

         The confusion stems from the fact that there are two watchdogs that operate in completely different ways. The device watchdog is capable of resetting the device. It is a simple free-running counter that needs to be cleared before it overflows and resets the device. The NMIWD counter is started only when certain events happen. When any of these events happen, the NMIWD counter starts running. If the NMI flag is not cleared by the software before this counter overflows, the NMIWD can also reset the device. I think the confusion is because there is a bit for the device watchdog in the NMIFLGFRC register even though it is strictly not part of the NMI mechanism. I am still working on how best to document this as it was a bit confusing for me as well.

  • +1 in reply to Hareesh Janakiraman
    TI__Guru* 95315 points
    Julia Li said:
    if customer set the NMIFLGFRC[CPU2 DRSn] bit to 1, will it cause the NMI of the CPU1 to interrupt and then cause the device to reset? 

    Yes.

    Julia Li said:
    2. If customer sets the NMIFLGFRC[CPU2 DRSn] bit to 1, will it cause the watchdog reset of CPU2 immediately? Or will it enable the watchdog of CPU2, then wait for the watchdog counter to overflow, and then reset the watchdog of CPU2?

    It will not cause a reset of CPU2. This NMIFLGFRC register is to just test the NMI logic by emulation.

    Julia Li said:
    3. Which bit of the CpuSysRegs.RESC register will be set to 1 if the above mentioned reset occurs? Is it the WDRSn bit or the NMIWDRSn bit?

    The RESC register for CPU1 will reflect the reset source as NMIWD.