TMS320F280049C: Atomic read of 32 bit int?

Actually, the answer to this question is more complicated than I suspected.  We have an action to figure this out, and then we'll post a more comprehensive response for you. Thanks!

This is still ambiguous.

Let me try to clarify the question:

in global context:

float F;
uint32_t int I;
uint32_t J;

uint

F = 1.0; // this write to F is  atomic as per answer to my previous question
if (F==1.0) // this is read of the value of F is atomic as per answer to my previous question (even though the evaluation of 'if' condition is not
I=1; // atomic as per manual
while (i==1) // it is not clear if the evaluation of the sub expression 'I' .e. reading of value from the global variable I is atomic or not. Of course the while condition as such is not atomic.
J = I; // is this atomic in the sense that I always get a consistent copy of I to J, ie. I either get the new value or old value if an interrupt changes I in the middle of this assigment and I do not get a value where half of the value of J is the old half of I and half is the new value of I

You can look at the recent discussion here:
https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1169583/launchxl-f28379d-atomic-operation-in-a-c-program/4427367?tisearch=e2e-sitesearch&keymatch=%20user%3A4124#4427367
There are some answers you are looking for.

Andy

Hello,

For your examples:
F=1.0;         // atomic write

if (F==1.0)   // F is already in R0H from above write and is not read again
                    // because it is not volatile. This expression is not atomic.

I=1;              // atomic write

while (I==1)  // I is already in a register from above write and is not read again
                     // because it is not volatile. The while expression is not atomic.

J = I;        // assignment is not atomic. uses two opcodes. atomic read, atomic write.
                // an interrupt could trigger between the read and the write.

We are updating our C28 optimization guide section on atomics with below details:
https://software-dl.ti.com/C2000/docs/optimization_guide/...atomic-access
2.4.9.1 Atomic Access:

• 16-bit reads/writes are atomic.  
• 32-bit float reads/writes are atomic except:  writing a 32-bit float constant is only atomic if performed with a single instruction.
• 32-bit integer reads/writes see “Additional notes”.

For other atomic operations, there are two recommended approaches:

• Use an atomic compiler intrinsic if one is available. These are documented in the compiler user’s guide (www.ti.com/lit/SPRU514). The description will say "in an atomic way".
• Disable / enable interrupts around atomic operations using below intrinsics:
       __disable_interrupts( );
       __enable_interrupts( );

Additional notes:

• 32-bit reads/writes that use a single instruction are atomic.  
• Atomic accesses within an ISR: By default, accesses within an ISR are atomic. The INTM bit is automatically set (disable interrupts) by the hardware during the context switch. The exception would be if the application re-enables interrupts within the ISR in order to nest interrupts.
• If possible, group atomic accesses together or create a function to perform the sequence disable-interrupts/atomic-accesses/enable-interrupts.

Regards,
Greg

Thank you Greg, it's always good that the conclusions from our forum discussions end up in some dedicated places. But I'm also counting that the same info will go to the future update of C/C++ Compiler Manual.

And one more thing. In the above optimization link and the code example we see:

    // If interrupts were originally enabled, re-enable them
    if (0U == (val & 0x1))
        __enable_interrupts();

Why not use __restore_interupts() intrinsic here? It would be easier.

Regards,
Andy