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TMS320F28388D: issue about ADC Zero Offset Calibration

Yale Li 李耀先
Expert 4660 points
Part Number: TMS320F28388D


Hi Team,

In step1, why is 112 step be added?

In step2, “Perform some multiple of 16 conversions on VREFLO”. Why multiple of 16?

Thanks & Regards,

Yale Li

  • +1
    TI__Mastermind 39170 points

    Hi Yale,

    Yale Li 李耀先 said:
    In step1, why is 112 step be added?

    Offset is 8-bit in 2's complement format.  The value in the OFFTRIM register is 16*Offset so 112 is 16*(7LSB).  Setting the offset to 7LSBs ensures that devices with natural offsets of negative LSBs will be accounted for in the calibration process described in the TRM.

    Yale Li 李耀先 said:
    In step2, “Perform some multiple of 16 conversions on VREFLO”. Why multiple of 16?

    Multiple of 16 allows for easier average calculation by simply shifting the accumulated results 4 bits to the right.

    Regards,

    Joseph